^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP54xx PRCM MPU instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "prcm_mpu_44xx_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP54XX_PRCM_MPU_BASE 0x48243000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* PRCM_MPU instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* PRCM_MPU clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * PRCM_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * point of view the PRCM_MPU is a single entity. It shares the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * programming model as the global PRCM and thus can be assimilate as two new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * MOD inside the PRCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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