^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP44xx PRCM MPU instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * or "OMAP4430".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "prcm_mpu_44xx_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP4430_PRCM_MPU_BASE 0x48243000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PRCM_MPU instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* PRCM_MPU clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * PRCM_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * point of view the PRCM_MPU is a single entity. It shares the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * programming model as the global PRCM and thus can be assimilate as two new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * MOD inside the PRCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP4_REVISION_PRCM_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* PRCM_MPU.DEVICE_PRM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* PRCM_MPU.CPU0 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* PRCM_MPU.CPU1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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