Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP4 PRCM_MPU module functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "prcm_mpu44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "cm-regbits-44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *   block registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct omap_domain_base prcm_mpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PRCM_MPU low-level functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	v = omap4_prcm_mpu_read_inst_reg(inst, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	v |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	omap4_prcm_mpu_write_inst_reg(v, inst, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  * omap2_set_globals_prcm_mpu - set the MPU PRCM base address (for early use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  * @prcm_mpu: PRCM_MPU base virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * XXX Will be replaced when the PRM/CM drivers are completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	prcm_mpu_base.va = prcm_mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }