Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * AM43x PRCM defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * version 2.  This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define AM43XX_PRM_PARTITION				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AM43XX_CM_PARTITION				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* PRM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AM43XX_PRM_OCP_SOCKET_INST			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AM43XX_PRM_MPU_INST				0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AM43XX_PRM_GFX_INST				0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AM43XX_PRM_RTC_INST				0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AM43XX_PRM_TAMPER_INST				0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AM43XX_PRM_CEFUSE_INST				0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AM43XX_PRM_PER_INST				0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AM43XX_PRM_WKUP_INST				0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AM43XX_PRM_DEVICE_INST				0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* PRM_IRQ offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AM43XX_PRM_IRQENABLE_MPU_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Other PRM offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AM43XX_PRM_IO_PMCTRL_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* RM RSTCTRL offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AM43XX_RM_PER_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AM43XX_RM_GFX_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AM43XX_RM_WKUP_RSTCTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* RM RSTST offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AM43XX_RM_GFX_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AM43XX_RM_PER_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AM43XX_RM_WKUP_RSTST_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* CM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AM43XX_CM_WKUP_INST				0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AM43XX_CM_DEVICE_INST				0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AM43XX_CM_DPLL_INST				0x4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AM43XX_CM_MPU_INST				0x8300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AM43XX_CM_GFX_INST				0x8400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AM43XX_CM_RTC_INST				0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AM43XX_CM_TAMPER_INST				0x8600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AM43XX_CM_CEFUSE_INST				0x8700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AM43XX_CM_PER_INST				0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* CD offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AM43XX_CM_WKUP_L3_AON_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AM43XX_CM_WKUP_WKUP_CDOFFS			0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AM43XX_CM_MPU_MPU_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AM43XX_CM_GFX_GFX_L3_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AM43XX_CM_RTC_RTC_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AM43XX_CM_TAMPER_TAMPER_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AM43XX_CM_PER_L3_CDOFFS				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AM43XX_CM_PER_L3S_CDOFFS			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AM43XX_CM_PER_ICSS_CDOFFS			0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AM43XX_CM_PER_L4LS_CDOFFS			0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AM43XX_CM_PER_EMIF_CDOFFS			0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AM43XX_CM_PER_LCDC_CDOFFS			0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define AM43XX_CM_PER_DSS_CDOFFS			0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AM43XX_CM_PER_CPSW_CDOFFS			0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AM43XX_CM_PER_OCPWP_L3_CDOFFS			0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* CLK CTRL offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET		0x0580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET		0x05a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x0448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x0478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x0488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x04a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x04b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x04b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x04c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x04c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET		0x04e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x0548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x0550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x0558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x0350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x0358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x0348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x0328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET               0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AM43XX_CM_PER_L3_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0b20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AM43XX_CM_PER_DES_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET		0x0560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET		0x0568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET		0x0570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET		0x0578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET		0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET		0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET		0x0458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET		0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET		0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x0490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET	0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET	0x05B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET        0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET	0x05C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET		0x0a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET		0x04a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif