^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * OMAP2/3 PRCM base and module definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2007-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Written by Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Module offsets from both CM_BASE & PRM_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Offsets that are the same on 24xx and 34xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OCP_MOD 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPU_MOD 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CORE_MOD 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GFX_MOD 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WKUP_MOD 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_MOD 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Chip-specific module offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP24XX_GR_MOD OCP_MOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP24XX_DSP_MOD 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP2430_MDM_MOD 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* IVA2 module is < base on 3430 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP3430_IVA2_MOD -0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP3430ES2_SGX_MOD GFX_MOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP3430_CCR_MOD PLL_MOD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP3430_DSS_MOD 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP3430_CAM_MOD 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP3430_PER_MOD 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP3430_EMU_MOD 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP3430_GR_MOD 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP3430_NEON_MOD 0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP3430ES2_USBHOST_MOD 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * TI81XX PRM module offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TI814X_PRM_DSP_MOD 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TI814X_PRM_HDVICP_MOD 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TI814X_PRM_ISP_MOD 0x0d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TI814X_PRM_HDVPSS_MOD 0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TI814X_PRM_GFX_MOD 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TI81XX_PRM_DEVICE_MOD 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TI816X_PRM_ACTIVE_MOD 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TI81XX_PRM_DEFAULT_MOD 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TI816X_PRM_IVAHD0_MOD 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TI816X_PRM_IVAHD1_MOD 0x0d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TI816X_PRM_IVAHD2_MOD 0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TI816X_PRM_SGX_MOD 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TI81XX_PRM_ALWON_MOD 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* 24XX register bits shared between CM & PRM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP2420_EN_MMC_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP2420_EN_MMC_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP24XX_EN_UART2_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP24XX_EN_UART2_MASK (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP24XX_EN_UART1_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP24XX_EN_UART1_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP24XX_EN_MCSPI2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP24XX_EN_MCSPI1_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP24XX_EN_MCBSP2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP24XX_EN_MCBSP1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP24XX_EN_GPT12_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP24XX_EN_GPT12_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP24XX_EN_GPT11_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP24XX_EN_GPT11_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP24XX_EN_GPT10_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP24XX_EN_GPT10_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP24XX_EN_GPT9_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP24XX_EN_GPT9_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP24XX_EN_GPT8_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP24XX_EN_GPT8_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP24XX_EN_GPT7_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP24XX_EN_GPT7_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP24XX_EN_GPT6_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP24XX_EN_GPT6_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP24XX_EN_GPT5_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP24XX_EN_GPT5_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP24XX_EN_GPT4_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP24XX_EN_GPT4_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP24XX_EN_GPT3_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP24XX_EN_GPT3_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP24XX_EN_GPT2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP24XX_EN_GPT2_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP2420_EN_VLYNQ_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP2420_EN_VLYNQ_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP2430_EN_GPIO5_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP2430_EN_GPIO5_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP2430_EN_MCSPI3_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP2430_EN_MCSPI3_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP2430_EN_MMCHS2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP2430_EN_MMCHS2_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP2430_EN_MMCHS1_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP2430_EN_MMCHS1_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP24XX_EN_UART3_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP24XX_EN_UART3_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP24XX_EN_USB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP24XX_EN_USB_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP2430_EN_MDM_INTC_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP2430_EN_USBHS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP2430_EN_USBHS_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP24XX_EN_GPMC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP24XX_EN_GPMC_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP2420_ST_MMC_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP2420_ST_MMC_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP24XX_ST_UART2_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP24XX_ST_UART2_MASK (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP24XX_ST_UART1_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP24XX_ST_UART1_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP24XX_ST_MCSPI2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP24XX_ST_MCSPI1_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP24XX_ST_MCBSP2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP24XX_ST_MCBSP1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP24XX_ST_GPT12_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP24XX_ST_GPT12_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP24XX_ST_GPT11_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP24XX_ST_GPT11_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP24XX_ST_GPT10_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP24XX_ST_GPT10_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP24XX_ST_GPT9_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP24XX_ST_GPT9_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP24XX_ST_GPT8_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP24XX_ST_GPT8_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP24XX_ST_GPT7_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP24XX_ST_GPT7_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP24XX_ST_GPT6_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP24XX_ST_GPT6_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP24XX_ST_GPT5_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP24XX_ST_GPT5_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP24XX_ST_GPT4_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP24XX_ST_GPT4_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP24XX_ST_GPT3_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP24XX_ST_GPT3_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP24XX_ST_GPT2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP24XX_ST_GPT2_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP2420_ST_VLYNQ_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP2420_ST_VLYNQ_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP2430_ST_MDM_INTC_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP2430_ST_GPIO5_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP2430_ST_GPIO5_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OMAP2430_ST_MCSPI3_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP2430_ST_MCSPI3_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP2430_ST_MMCHS2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP2430_ST_MMCHS2_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP2430_ST_MMCHS1_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP2430_ST_MMCHS1_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP2430_ST_USBHS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP2430_ST_USBHS_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP24XX_ST_UART3_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP24XX_ST_UART3_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP24XX_ST_USB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP24XX_ST_USB_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP24XX_EN_GPIOS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP24XX_EN_GPIOS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP24XX_EN_GPT1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP24XX_EN_GPT1_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP24XX_ST_GPIOS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP24XX_ST_GPIOS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP24XX_ST_32KSYNC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP24XX_ST_GPT1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP24XX_ST_GPT1_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP2430_ST_MDM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP2430_ST_MDM_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* 3430 register bits shared between CM & PRM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* CM_REVISION, PRM_REVISION shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP3430_REV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP3430_REV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP3430_AUTOIDLE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP3430_EN_MMC3_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP3430_EN_MMC3_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP3430_EN_MMC2_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP3430_EN_MMC2_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP3430_EN_MMC1_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OMAP3430_EN_MMC1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AM35XX_EN_UART4_MASK (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AM35XX_EN_UART4_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP3430_EN_MCSPI4_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP3430_EN_MCSPI4_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OMAP3430_EN_MCSPI3_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OMAP3430_EN_MCSPI3_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP3430_EN_MCSPI2_MASK (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP3430_EN_MCSPI2_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OMAP3430_EN_MCSPI1_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP3430_EN_MCSPI1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OMAP3430_EN_I2C3_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OMAP3430_EN_I2C3_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP3430_EN_I2C2_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OMAP3430_EN_I2C2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OMAP3430_EN_I2C1_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OMAP3430_EN_I2C1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OMAP3430_EN_UART2_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OMAP3430_EN_UART2_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP3430_EN_UART1_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP3430_EN_UART1_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OMAP3430_EN_GPT11_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP3430_EN_GPT11_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OMAP3430_EN_GPT10_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define OMAP3430_EN_GPT10_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OMAP3430_EN_MCBSP5_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OMAP3430_EN_MCBSP5_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define OMAP3430_EN_MCBSP1_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define OMAP3430_EN_MCBSP1_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OMAP3430_EN_FSHOSTUSB_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define OMAP3430_EN_D2D_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define OMAP3430_EN_D2D_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OMAP3430_EN_HSOTGUSB_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define OMAP3430_EN_HSOTGUSB_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OMAP3430_ST_MMC3_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define OMAP3430_ST_MMC3_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OMAP3430_ST_MMC2_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OMAP3430_ST_MMC2_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OMAP3430_ST_MMC1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define OMAP3430_ST_MMC1_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OMAP3430_ST_MCSPI4_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define OMAP3430_ST_MCSPI4_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OMAP3430_ST_MCSPI3_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP3430_ST_MCSPI3_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OMAP3430_ST_MCSPI2_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OMAP3430_ST_MCSPI2_MASK (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP3430_ST_MCSPI1_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OMAP3430_ST_MCSPI1_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OMAP3430_ST_I2C3_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OMAP3430_ST_I2C3_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OMAP3430_ST_I2C2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OMAP3430_ST_I2C2_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OMAP3430_ST_I2C1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OMAP3430_ST_I2C1_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OMAP3430_ST_UART2_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OMAP3430_ST_UART2_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OMAP3430_ST_UART1_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OMAP3430_ST_UART1_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OMAP3430_ST_GPT11_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define OMAP3430_ST_GPT11_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OMAP3430_ST_GPT10_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OMAP3430_ST_GPT10_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define OMAP3430_ST_MCBSP5_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OMAP3430_ST_MCBSP5_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OMAP3430_ST_MCBSP1_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OMAP3430_ST_MCBSP1_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OMAP3430_ST_D2D_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OMAP3430_ST_D2D_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define OMAP3430_EN_GPIO1_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OMAP3430_EN_GPIO1_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OMAP3430_EN_GPT12_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OMAP3430_EN_GPT12_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define OMAP3430_EN_GPT1_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define OMAP3430_EN_GPT1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define OMAP3430_EN_SR2_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define OMAP3430_EN_SR2_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OMAP3430_EN_SR1_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OMAP3430_EN_SR1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define OMAP3430_EN_GPT12_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OMAP3430_EN_GPT12_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define OMAP3430_ST_SR2_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OMAP3430_ST_SR2_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OMAP3430_ST_SR1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OMAP3430_ST_SR1_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define OMAP3430_ST_GPIO1_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OMAP3430_ST_GPIO1_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP3430_ST_32KSYNC_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OMAP3430_ST_32KSYNC_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OMAP3430_ST_GPT12_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OMAP3430_ST_GPT12_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define OMAP3430_ST_GPT1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define OMAP3430_ST_GPT1_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OMAP3430_EN_MPU_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define OMAP3430_EN_MPU_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OMAP3630_EN_UART4_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define OMAP3630_EN_UART4_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define OMAP3430_EN_GPIO6_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define OMAP3430_EN_GPIO6_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define OMAP3430_EN_GPIO5_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define OMAP3430_EN_GPIO5_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OMAP3430_EN_GPIO4_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OMAP3430_EN_GPIO4_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OMAP3430_EN_GPIO3_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OMAP3430_EN_GPIO3_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OMAP3430_EN_GPIO2_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OMAP3430_EN_GPIO2_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OMAP3430_EN_UART3_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OMAP3430_EN_UART3_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OMAP3430_EN_GPT9_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define OMAP3430_EN_GPT9_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OMAP3430_EN_GPT8_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OMAP3430_EN_GPT8_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OMAP3430_EN_GPT7_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OMAP3430_EN_GPT7_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OMAP3430_EN_GPT6_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OMAP3430_EN_GPT6_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OMAP3430_EN_GPT5_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OMAP3430_EN_GPT5_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OMAP3430_EN_GPT4_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OMAP3430_EN_GPT4_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OMAP3430_EN_GPT3_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OMAP3430_EN_GPT3_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OMAP3430_EN_GPT2_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OMAP3430_EN_GPT2_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * be ST_* bits instead? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OMAP3430_EN_MCBSP4_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OMAP3430_EN_MCBSP4_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OMAP3430_EN_MCBSP3_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OMAP3430_EN_MCBSP3_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define OMAP3430_EN_MCBSP2_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OMAP3430_EN_MCBSP2_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* CM_IDLEST_PER, PM_WKST_PER shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OMAP3630_ST_UART4_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OMAP3630_ST_UART4_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define OMAP3430_ST_GPIO6_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define OMAP3430_ST_GPIO6_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define OMAP3430_ST_GPIO5_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define OMAP3430_ST_GPIO5_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define OMAP3430_ST_GPIO4_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define OMAP3430_ST_GPIO4_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OMAP3430_ST_GPIO3_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define OMAP3430_ST_GPIO3_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define OMAP3430_ST_GPIO2_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define OMAP3430_ST_GPIO2_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define OMAP3430_ST_UART3_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define OMAP3430_ST_UART3_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define OMAP3430_ST_GPT9_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define OMAP3430_ST_GPT9_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define OMAP3430_ST_GPT8_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define OMAP3430_ST_GPT8_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define OMAP3430_ST_GPT7_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define OMAP3430_ST_GPT7_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define OMAP3430_ST_GPT6_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define OMAP3430_ST_GPT6_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define OMAP3430_ST_GPT5_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define OMAP3430_ST_GPT5_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define OMAP3430_ST_GPT4_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define OMAP3430_ST_GPT4_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define OMAP3430_ST_GPT3_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define OMAP3430_ST_GPT3_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define OMAP3430_ST_GPT2_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define OMAP3430_ST_GPT2_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define OMAP3430_EN_CORE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define OMAP3430_EN_CORE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Maximum time(us) it takes to output the signal WUCLKOUT of the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * pad of the I/O ring after asserting WUCLKIN high. Tero measured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * microseconds on OMAP4, so this timeout may be too high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MAX_IOPAD_LATCH_TIME 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) # ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * omap_test_timeout - busy-loop, testing a condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @cond: condition to test until it evaluates to true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @timeout: maximum number of microseconds in the timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @index: loop index (integer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Loop waiting for @cond to become true or until at least @timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * microseconds have passed. To use, define some integer @index in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * calling code. After running, if @index == @timeout, then the loop has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * timed out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define omap_test_timeout(cond, timeout, index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (index = 0; index < timeout; index++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (cond) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) udelay(1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * struct omap_prcm_irq - describes a PRCM interrupt bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * @priority: should this interrupt be handled before @priority=false IRQs?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * On systems with multiple PRM MPU IRQ registers, the bitfields read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * the registers are concatenated, so @offset could be > 31 on these systems -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * see omap_prm_irq_handler() for more details. I/O ring interrupts should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * have @priority set to true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct omap_prcm_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bool priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * struct omap_prcm_irq_setup - PRCM interrupt controller details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * @nr_irqs: number of entries in the @irqs array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @irq: MPU IRQ asserted when a PRCM interrupt arrives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * @ocp_barrier: fn ptr to force buffered PRM writes to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * @restore_irqen: fn ptr to save and clear IRQENABLE regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * @reconfigure_io_chain: fn ptr to reconfigure IO chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * @saved_mask: IRQENABLE regs are saved here during suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * @suspended: set to true after Linux suspend code has called our ->prepare()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * @saved_mask, @priority_mask, @base_irq, @suspended, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @suspend_save_flag are populated dynamically, and are not to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * specified in static initializers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct omap_prcm_irq_setup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u16 pm_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 nr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const struct omap_prcm_irq *irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void (*read_pending_irqs)(unsigned long *events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void (*ocp_barrier)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void (*save_and_clear_irqen)(u32 *saved_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) void (*restore_irqen)(u32 *saved_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void (*reconfigure_io_chain)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 *saved_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 *priority_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int base_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bool suspend_save_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define OMAP_PRCM_IRQ(_name, _offset, _priority) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .priority = _priority \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct omap_domain_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void __iomem *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) s16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * struct omap_prcm_init_data - PRCM driver init data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * @index: clock memory mapping index to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @mem: IO mem pointer for this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @phys: IO mem physical base address for this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @offset: module base address offset from the IO base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * @flags: PRCM module init flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * @device_inst_offset: device instance offset within the module address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @init: low level PRCM init function for this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @np: device node for this PRCM module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct omap_prcm_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) s16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) s32 device_inst_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int (*init)(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) extern void omap_prcm_irq_cleanup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) extern int omap_prcm_register_chain_handler(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct omap_prcm_irq_setup *irq_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) extern int omap_prcm_event_to_irq(const char *event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) extern void omap_prcm_irq_prepare(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) extern void omap_prcm_irq_complete(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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