^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRA7xx Power domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Abhijit Pagare (abhijitpagare@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "prm7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "prcm_mpu7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* iva_7xx_pwrdm: IVA-HD power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct powerdomain iva_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = "iva_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .prcm_offs = DRA7XX_PRM_IVA_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .banks = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [0] = PWRSTS_ON, /* hwa_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [1] = PWRSTS_ON, /* sl2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [2] = PWRSTS_ON, /* tcm1_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [3] = PWRSTS_ON, /* tcm2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* rtc_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct powerdomain rtc_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "rtc_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .prcm_offs = DRA7XX_PRM_RTC_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* custefuse_7xx_pwrdm: Customer efuse controller power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct powerdomain custefuse_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "custefuse_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct powerdomain custefuse_aon_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "custefuse_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ipu_7xx_pwrdm: Audio back end power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct powerdomain ipu_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "ipu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .prcm_offs = DRA7XX_PRM_IPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [0] = PWRSTS_ON, /* aessmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [1] = PWRSTS_ON, /* periphmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* dss_7xx_pwrdm: Display subsystem power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct powerdomain dss_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "dss_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .prcm_offs = DRA7XX_PRM_DSS_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [0] = PWRSTS_ON, /* dss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* l4per_7xx_pwrdm: Target peripherals power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct powerdomain l4per_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "l4per_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .prcm_offs = DRA7XX_PRM_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [0] = PWRSTS_ON, /* nonretained_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [1] = PWRSTS_ON, /* retained_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* gpu_7xx_pwrdm: 3D accelerator power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct powerdomain gpu_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "gpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .prcm_offs = DRA7XX_PRM_GPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [0] = PWRSTS_ON, /* gpu_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* wkupaon_7xx_pwrdm: Wake-up power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct powerdomain wkupaon_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "wkupaon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [0] = PWRSTS_ON, /* wkup_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* core_7xx_pwrdm: CORE power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct powerdomain core_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .prcm_offs = DRA7XX_PRM_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .banks = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [0] = PWRSTS_ON, /* core_nret_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [1] = PWRSTS_ON, /* core_ocmram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [2] = PWRSTS_ON, /* core_other_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [3] = PWRSTS_ON, /* ipu_l2ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [4] = PWRSTS_ON, /* ipu_unicache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct powerdomain coreaon_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "coreaon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .prcm_offs = DRA7XX_PRM_COREAON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct powerdomain cpu0_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "cpu0_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [0] = PWRSTS_ON, /* cpu0_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct powerdomain cpu1_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "cpu1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [0] = PWRSTS_ON, /* cpu1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* vpe_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct powerdomain vpe_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "vpe_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .prcm_offs = DRA7XX_PRM_VPE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [0] = PWRSTS_ON, /* vpe_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct powerdomain mpu_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "mpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .prcm_offs = DRA7XX_PRM_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [0] = PWRSTS_OFF_RET, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [1] = PWRSTS_RET, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [0] = PWRSTS_ON, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [1] = PWRSTS_ON, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct powerdomain l3init_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .name = "l3init_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .prcm_offs = DRA7XX_PRM_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [0] = PWRSTS_ON, /* gmac_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [1] = PWRSTS_ON, /* l3init_bank1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [2] = PWRSTS_ON, /* l3init_bank2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* eve3_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct powerdomain eve3_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .name = "eve3_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .prcm_offs = DRA7XX_PRM_EVE3_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [0] = PWRSTS_ON, /* eve3_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* emu_7xx_pwrdm: Emulation power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct powerdomain emu_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "emu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .prcm_offs = DRA7XX_PRM_EMU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [0] = PWRSTS_ON, /* emu_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* dsp2_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct powerdomain dsp2_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "dsp2_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .prcm_offs = DRA7XX_PRM_DSP2_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [0] = PWRSTS_ON, /* dsp2_edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [1] = PWRSTS_ON, /* dsp2_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [2] = PWRSTS_ON, /* dsp2_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* dsp1_7xx_pwrdm: Tesla processor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct powerdomain dsp1_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "dsp1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .prcm_offs = DRA7XX_PRM_DSP1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [0] = PWRSTS_ON, /* dsp1_edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [1] = PWRSTS_ON, /* dsp1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [2] = PWRSTS_ON, /* dsp1_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* cam_7xx_pwrdm: Camera subsystem power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct powerdomain cam_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "cam_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .prcm_offs = DRA7XX_PRM_CAM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [0] = PWRSTS_ON, /* vip_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* eve4_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct powerdomain eve4_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .name = "eve4_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .prcm_offs = DRA7XX_PRM_EVE4_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [0] = PWRSTS_ON, /* eve4_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* eve2_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct powerdomain eve2_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "eve2_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .prcm_offs = DRA7XX_PRM_EVE2_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [0] = PWRSTS_ON, /* eve2_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* eve1_7xx_pwrdm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct powerdomain eve1_7xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "eve1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .prcm_offs = DRA7XX_PRM_EVE1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [0] = PWRSTS_ON, /* eve1_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * The following power domains are not under SW control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * mpuaon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * mmaon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* As powerdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct powerdomain *powerdomains_dra7xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) &iva_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) &rtc_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) &ipu_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) &dss_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) &l4per_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &gpu_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &wkupaon_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &core_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &coreaon_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &cpu0_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &cpu1_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &vpe_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) &mpu_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &l3init_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) &eve3_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) &emu_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) &dsp2_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) &dsp1_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) &cam_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) &eve4_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) &eve2_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) &eve1_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct powerdomain *powerdomains_dra76x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) &custefuse_aon_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct powerdomain *powerdomains_dra74x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) &custefuse_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct powerdomain *powerdomains_dra72x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &custefuse_aon_7xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void __init dra7xx_powerdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pwrdm_register_pwrdms(powerdomains_dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (soc_is_dra76x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pwrdm_register_pwrdms(powerdomains_dra76x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else if (soc_is_dra74x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pwrdm_register_pwrdms(powerdomains_dra74x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else if (soc_is_dra72x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pwrdm_register_pwrdms(powerdomains_dra72x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pwrdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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