Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP54XX Power domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Abhijit Pagare (abhijitpagare@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "prm54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "prcm_mpu54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* core_54xx_pwrdm: CORE power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static struct powerdomain core_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.name		  = "core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.prcm_offs	  = OMAP54XX_PRM_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.pwrsts		  = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	.banks		  = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* abe_54xx_pwrdm: Audio back end power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static struct powerdomain abe_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.name		  = "abe_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.prcm_offs	  = OMAP54XX_PRM_ABE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.pwrsts		  = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.pwrsts_logic_ret = PWRSTS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.banks		  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		[0] = PWRSTS_OFF_RET,	/* aessmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		[1] = PWRSTS_OFF_RET,	/* periphmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		[0] = PWRSTS_OFF_RET,	/* aessmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		[1] = PWRSTS_OFF_RET,	/* periphmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static struct powerdomain coreaon_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.name		  = "coreaon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.prcm_offs	  = OMAP54XX_PRM_COREAON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.pwrsts		  = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* dss_54xx_pwrdm: Display subsystem power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct powerdomain dss_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.name		  = "dss_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.prcm_offs	  = OMAP54XX_PRM_DSS_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.pwrsts		  = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.pwrsts_logic_ret = PWRSTS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		[0] = PWRSTS_OFF_RET,	/* dss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		[0] = PWRSTS_OFF_RET,	/* dss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct powerdomain cpu0_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.name		  = "cpu0_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.voltdm		  = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.prcm_offs	  = OMAP54XX_PRCM_MPU_PRM_C0_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.pwrsts		  = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		[0] = PWRSTS_ON,	/* cpu0_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct powerdomain cpu1_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.name		  = "cpu1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.voltdm		  = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.prcm_offs	  = OMAP54XX_PRCM_MPU_PRM_C1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.pwrsts		  = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		[0] = PWRSTS_ON,	/* cpu1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* emu_54xx_pwrdm: Emulation power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct powerdomain emu_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.name		  = "emu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.voltdm		  = { .name = "wkup" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.prcm_offs	  = OMAP54XX_PRM_EMU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.pwrsts		  = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		[0] = PWRSTS_OFF_RET,	/* emu_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		[0] = PWRSTS_OFF_RET,	/* emu_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct powerdomain mpu_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name		  = "mpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.voltdm		  = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.prcm_offs	  = OMAP54XX_PRM_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.pwrsts		  = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.banks		  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		[1] = PWRSTS_RET,	/* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		[1] = PWRSTS_OFF_RET,	/* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* custefuse_54xx_pwrdm: Customer efuse controller power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct powerdomain custefuse_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.name		  = "custefuse_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.prcm_offs	  = OMAP54XX_PRM_CUSTEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.pwrsts		  = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* dsp_54xx_pwrdm: Tesla processor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct powerdomain dsp_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.name		  = "dsp_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.voltdm		  = { .name = "mm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.prcm_offs	  = OMAP54XX_PRM_DSP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.pwrsts		  = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.banks		  = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		[0] = PWRSTS_OFF_RET,	/* dsp_edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		[1] = PWRSTS_OFF_RET,	/* dsp_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		[2] = PWRSTS_OFF_RET,	/* dsp_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		[0] = PWRSTS_OFF_RET,	/* dsp_edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		[1] = PWRSTS_OFF_RET,	/* dsp_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		[2] = PWRSTS_OFF_RET,	/* dsp_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* cam_54xx_pwrdm: Camera subsystem power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct powerdomain cam_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.name		  = "cam_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.prcm_offs	  = OMAP54XX_PRM_CAM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.pwrsts		  = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		[0] = PWRSTS_OFF_RET,	/* cam_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		[0] = PWRSTS_OFF_RET,	/* cam_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct powerdomain l3init_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.name		  = "l3init_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.voltdm		  = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.prcm_offs	  = OMAP54XX_PRM_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.pwrsts		  = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.banks		  = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		[0] = PWRSTS_OFF_RET,	/* l3init_bank1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		[1] = PWRSTS_OFF_RET,	/* l3init_bank2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		[0] = PWRSTS_OFF_RET,	/* l3init_bank1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		[1] = PWRSTS_OFF_RET,	/* l3init_bank2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* gpu_54xx_pwrdm: 3D accelerator power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct powerdomain gpu_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.name		  = "gpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.voltdm		  = { .name = "mm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.prcm_offs	  = OMAP54XX_PRM_GPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.pwrsts		  = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* wkupaon_54xx_pwrdm: Wake-up power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct powerdomain wkupaon_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.name		  = "wkupaon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.voltdm		  = { .name = "wkup" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.prcm_offs	  = OMAP54XX_PRM_WKUPAON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.pwrsts		  = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.banks		  = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		[0] = PWRSTS_ON,	/* wkup_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* iva_54xx_pwrdm: IVA-HD power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct powerdomain iva_54xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.name		  = "iva_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.voltdm		  = { .name = "mm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.prcm_offs	  = OMAP54XX_PRM_IVA_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.pwrsts		  = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.pwrsts_logic_ret = PWRSTS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.banks		  = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.pwrsts_mem_ret	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.pwrsts_mem_on	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  * The following power domains are not under SW control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * mpuaon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * mmaon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* As powerdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct powerdomain *powerdomains_omap54xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	&core_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	&abe_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	&coreaon_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	&dss_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	&cpu0_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	&cpu1_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	&emu_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	&mpu_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	&custefuse_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	&dsp_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	&cam_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	&l3init_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	&gpu_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	&wkupaon_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	&iva_54xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void __init omap54xx_powerdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	pwrdm_register_pwrdms(powerdomains_omap54xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	pwrdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }