^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP4 Power domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Abhijit Pagare (abhijitpagare@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "prm-regbits-44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "prm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "prcm_mpu44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* core_44xx_pwrdm: CORE power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct powerdomain core_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .name = "core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .prcm_offs = OMAP4430_PRM_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .banks = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [0] = PWRSTS_OFF, /* core_nret_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [1] = PWRSTS_RET, /* core_ocmram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [2] = PWRSTS_RET, /* core_other_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [4] = PWRSTS_OFF_RET, /* ducati_unicache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [0] = PWRSTS_ON, /* core_nret_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [1] = PWRSTS_ON, /* core_ocmram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [2] = PWRSTS_ON, /* core_other_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [3] = PWRSTS_ON, /* ducati_l2ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [4] = PWRSTS_ON, /* ducati_unicache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* gfx_44xx_pwrdm: 3D accelerator power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct powerdomain gfx_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "gfx_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .prcm_offs = OMAP4430_PRM_GFX_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [0] = PWRSTS_OFF, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [0] = PWRSTS_ON, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* abe_44xx_pwrdm: Audio back end power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct powerdomain abe_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "abe_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .voltdm = { .name = "iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .prcm_offs = OMAP4430_PRM_ABE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .pwrsts_logic_ret = PWRSTS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [0] = PWRSTS_RET, /* aessmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [1] = PWRSTS_OFF, /* periphmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [0] = PWRSTS_ON, /* aessmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [1] = PWRSTS_ON, /* periphmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* dss_44xx_pwrdm: Display subsystem power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct powerdomain dss_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "dss_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .prcm_offs = OMAP4430_PRM_DSS_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .pwrsts_logic_ret = PWRSTS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [0] = PWRSTS_OFF, /* dss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [0] = PWRSTS_ON, /* dss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* tesla_44xx_pwrdm: Tesla processor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct powerdomain tesla_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "tesla_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .voltdm = { .name = "iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .prcm_offs = OMAP4430_PRM_TESLA_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [0] = PWRSTS_RET, /* tesla_edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [1] = PWRSTS_OFF_RET, /* tesla_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [2] = PWRSTS_OFF_RET, /* tesla_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [0] = PWRSTS_ON, /* tesla_edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [1] = PWRSTS_ON, /* tesla_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [2] = PWRSTS_ON, /* tesla_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* wkup_44xx_pwrdm: Wake-up power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct powerdomain wkup_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "wkup_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .voltdm = { .name = "wakeup" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .prcm_offs = OMAP4430_PRM_WKUP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [0] = PWRSTS_OFF, /* wkup_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [0] = PWRSTS_ON, /* wkup_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct powerdomain cpu0_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "cpu0_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .voltdm = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [0] = PWRSTS_ON, /* cpu0_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct powerdomain cpu1_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "cpu1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .voltdm = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [0] = PWRSTS_ON, /* cpu1_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* emu_44xx_pwrdm: Emulation power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct powerdomain emu_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "emu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .voltdm = { .name = "wakeup" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .prcm_offs = OMAP4430_PRM_EMU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [0] = PWRSTS_OFF, /* emu_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [0] = PWRSTS_ON, /* emu_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct powerdomain mpu_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "mpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .voltdm = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .prcm_offs = OMAP4430_PRM_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [0] = PWRSTS_OFF_RET, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [1] = PWRSTS_OFF_RET, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [2] = PWRSTS_RET, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [0] = PWRSTS_ON, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [1] = PWRSTS_ON, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [2] = PWRSTS_ON, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* ivahd_44xx_pwrdm: IVA-HD power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct powerdomain ivahd_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "ivahd_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .voltdm = { .name = "iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .prcm_offs = OMAP4430_PRM_IVAHD_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .pwrsts_logic_ret = PWRSTS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .banks = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [0] = PWRSTS_OFF, /* hwa_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [1] = PWRSTS_OFF_RET, /* sl2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [2] = PWRSTS_OFF_RET, /* tcm1_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [3] = PWRSTS_OFF_RET, /* tcm2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [0] = PWRSTS_ON, /* hwa_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [1] = PWRSTS_ON, /* sl2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [2] = PWRSTS_ON, /* tcm1_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [3] = PWRSTS_ON, /* tcm2_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* cam_44xx_pwrdm: Camera subsystem power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct powerdomain cam_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .name = "cam_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .prcm_offs = OMAP4430_PRM_CAM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [0] = PWRSTS_OFF, /* cam_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [0] = PWRSTS_ON, /* cam_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct powerdomain l3init_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .name = "l3init_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .prcm_offs = OMAP4430_PRM_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [0] = PWRSTS_OFF, /* l3init_bank1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [0] = PWRSTS_ON, /* l3init_bank1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* l4per_44xx_pwrdm: Target peripherals power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct powerdomain l4per_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "l4per_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .prcm_offs = OMAP4430_PRM_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .pwrsts = PWRSTS_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [0] = PWRSTS_OFF, /* nonretained_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [1] = PWRSTS_RET, /* retained_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [0] = PWRSTS_ON, /* nonretained_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [1] = PWRSTS_ON, /* retained_bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct powerdomain always_on_core_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "always_on_core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct powerdomain cefuse_44xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "cefuse_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .prcm_offs = OMAP4430_PRM_CEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * The following power domains are not under SW control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * always_on_iva
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * always_on_mpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * stdefuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* As powerdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct powerdomain *powerdomains_omap44xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &core_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &gfx_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &abe_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &dss_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &tesla_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) &wkup_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) &cpu0_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) &cpu1_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &emu_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) &mpu_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) &ivahd_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &cam_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) &l3init_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &l4per_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) &always_on_core_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &cefuse_44xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __init omap44xx_powerdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pwrdm_register_pwrdms(powerdomains_omap44xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pwrdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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