^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP3 powerdomain definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley, Jouni Högander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "powerdomains2xxx_3xxx_data.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "prm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 34XX-specific powerdomains, dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Powerdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct powerdomain iva2_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = "iva2_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .prcm_offs = OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .banks = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [0] = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [1] = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [2] = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [3] = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [0] = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [1] = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [2] = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [3] = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct powerdomain mpu_3xxx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "mpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .prcm_offs = MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .flags = PWRDM_HAS_MPU_QUIRK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [0] = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [0] = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct powerdomain mpu_am35x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = "mpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .prcm_offs = MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pwrsts_logic_ret = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = PWRDM_HAS_MPU_QUIRK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [0] = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [0] = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * The USBTLL Save-and-Restore mechanism is broken on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * needs to be disabled on these chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Refer: 3430 errata ID i459 and 3630 errata ID i579
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Note: setting the SAR flag could help for errata ID i478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * which applies to 3430 <= ES3.1, but since the SAR feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * is broken, do not use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .prcm_offs = CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct powerdomain core_3xxx_es3_1_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .prcm_offs = CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Setting the SAR flag for errata ID i478 which applies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * to 3430 <= ES3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct powerdomain core_am35x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "core_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .prcm_offs = CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .pwrsts_logic_ret = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [0] = PWRSTS_ON, /* MEM1RETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [1] = PWRSTS_ON, /* MEM2RETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [0] = PWRSTS_ON, /* MEM1ONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [1] = PWRSTS_ON, /* MEM2ONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct powerdomain dss_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .name = "dss_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .prcm_offs = OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [0] = PWRSTS_RET, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct powerdomain dss_am35x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .name = "dss_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .prcm_offs = OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .pwrsts_logic_ret = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [0] = PWRSTS_ON, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * possible SGX powerstate, the SGX device itself does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * retention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct powerdomain sgx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .name = "sgx_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .prcm_offs = OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* XXX This is accurate for 3430 SGX, but what about GFX? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [0] = PWRSTS_RET, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct powerdomain sgx_am35x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = "sgx_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .prcm_offs = OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .pwrsts_logic_ret = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [0] = PWRSTS_ON, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct powerdomain cam_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "cam_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .prcm_offs = OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [0] = PWRSTS_RET, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct powerdomain per_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "per_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .prcm_offs = OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [0] = PWRSTS_RET, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct powerdomain per_am35x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "per_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .prcm_offs = OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .pwrsts_logic_ret = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [0] = PWRSTS_ON, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct powerdomain emu_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .name = "emu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .prcm_offs = OMAP3430_EMU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct powerdomain neon_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "neon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .prcm_offs = OMAP3430_NEON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct powerdomain neon_am35x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "neon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .prcm_offs = OMAP3430_NEON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .pwrsts_logic_ret = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct powerdomain usbhost_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "usbhost_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .prcm_offs = OMAP3430ES2_USBHOST_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .pwrsts_logic_ret = PWRSTS_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * REVISIT: Enabling usb host save and restore mechanism seems to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * leave the usb host domain permanently in ACTIVE mode after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * changing the usb host power domain state from OFF to active once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Disabling for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [0] = PWRSTS_RET, /* MEMRETSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [0] = PWRSTS_ON, /* MEMONSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct powerdomain dpll1_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "dpll1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .prcm_offs = MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct powerdomain dpll2_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "dpll2_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .prcm_offs = OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct powerdomain dpll3_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .name = "dpll3_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .prcm_offs = PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct powerdomain dpll4_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "dpll4_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .prcm_offs = PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct powerdomain dpll5_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = "dpll5_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .prcm_offs = PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct powerdomain alwon_81xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "alwon_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .prcm_offs = TI81XX_PRM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct powerdomain device_81xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "device_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .prcm_offs = TI81XX_PRM_DEVICE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct powerdomain gem_814x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "gem_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .prcm_offs = TI814X_PRM_DSP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .voltdm = { .name = "dsp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct powerdomain ivahd_814x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "ivahd_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .prcm_offs = TI814X_PRM_HDVICP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .voltdm = { .name = "iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct powerdomain hdvpss_814x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "hdvpss_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .prcm_offs = TI814X_PRM_HDVPSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .voltdm = { .name = "dsp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct powerdomain sgx_814x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "sgx_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .prcm_offs = TI814X_PRM_GFX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct powerdomain isp_814x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "isp_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .prcm_offs = TI814X_PRM_ISP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct powerdomain active_81xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "active_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .prcm_offs = TI816X_PRM_ACTIVE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct powerdomain default_81xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .name = "default_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .prcm_offs = TI81XX_PRM_DEFAULT_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct powerdomain ivahd0_816x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .name = "ivahd0_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .prcm_offs = TI816X_PRM_IVAHD0_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct powerdomain ivahd1_816x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "ivahd1_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .prcm_offs = TI816X_PRM_IVAHD1_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct powerdomain ivahd2_816x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "ivahd2_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .prcm_offs = TI816X_PRM_IVAHD2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .voltdm = { .name = "mpu_iva" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct powerdomain sgx_816x_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .name = "sgx_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .prcm_offs = TI816X_PRM_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* As powerdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &wkup_omap2_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &iva2_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &mpu_3xxx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &neon_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &cam_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &dss_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &per_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &emu_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &dpll1_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &dpll2_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &dpll3_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &dpll4_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &gfx_omap2_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &core_3xxx_pre_es3_1_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* also includes 3630ES1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &core_3xxx_pre_es3_1_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &sgx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) &usbhost_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) &dpll5_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* also includes 3630ES1.1+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &core_3xxx_es3_1_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) &sgx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &usbhost_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) &dpll5_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct powerdomain *powerdomains_am35x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &wkup_omap2_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &mpu_am35x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &neon_am35x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &core_am35x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &sgx_am35x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &dss_am35x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &per_am35x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &emu_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &dpll1_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &dpll3_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) &dpll4_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &dpll5_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct powerdomain *powerdomains_ti814x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &alwon_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &device_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &active_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &default_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &gem_814x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &ivahd_814x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &hdvpss_814x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &sgx_814x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &isp_814x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static struct powerdomain *powerdomains_ti816x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) &alwon_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &device_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) &active_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &default_81xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) &ivahd0_816x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &ivahd1_816x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &ivahd2_816x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &sgx_816x_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* TI81XX specific ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define TI81XX_PM_PWSTCTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define TI81XX_RM_RSTCTRL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define TI81XX_PM_PWSTST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (pwrst << OMAP_POWERSTATE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) TI81XX_PM_PWSTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) OMAP_POWERSTATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) TI81XX_PM_PWSTST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) OMAP_POWERSTATEST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) TI81XX_PM_PWSTST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) OMAP3430_LOGICSTATEST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) (pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) TI81XX_PM_PWSTST) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) OMAP_INTRANSITION_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (c++ < PWRDM_TRANSITION_BAILOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (c > PWRDM_TRANSITION_BAILOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pr_err("powerdomain: %s timeout waiting for transition\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pwrdm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pr_debug("powerdomain: completed transition in %d loops\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct pwrdm_ops ti81xx_pwrdm_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void __init omap3xxx_powerdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Only 81xx needs custom pwrdm_operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!cpu_is_ti81xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rev = omap_rev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pwrdm_register_pwrdms(powerdomains_am35x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) rev == TI8148_REV_ES2_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pwrdm_register_pwrdms(powerdomains_ti814x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pwrdm_register_pwrdms(powerdomains_ti816x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pwrdm_register_pwrdms(powerdomains_omap3430_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case OMAP3430_REV_ES1_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pwrdm_register_pwrdms(powerdomains_omap3430es1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case OMAP3430_REV_ES2_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) case OMAP3430_REV_ES2_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case OMAP3430_REV_ES3_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case OMAP3630_REV_ES1_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case OMAP3430_REV_ES3_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case OMAP3430_REV_ES3_1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case OMAP3630_REV_ES1_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case OMAP3630_REV_ES1_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pwrdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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