^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AM33XX Power domain data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "prm-regbits-33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct powerdomain gfx_33xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .name = "gfx_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .prcm_offs = AM33XX_PRM_GFX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .banks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .mem_on_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .mem_ret_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .mem_pwrst_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .mem_retst_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [0] = PWRSTS_OFF_RET, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [0] = PWRSTS_ON, /* gfx_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct powerdomain rtc_33xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = "rtc_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .voltdm = { .name = "rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .prcm_offs = AM33XX_PRM_RTC_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct powerdomain wkup_33xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "wkup_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .prcm_offs = AM33XX_PRM_WKUP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .pwrsts = PWRSTS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct powerdomain per_33xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .name = "per_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .prcm_offs = AM33XX_PRM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .mem_on_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mem_ret_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .mem_pwrst_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .mem_retst_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [0] = PWRSTS_OFF_RET, /* pruss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [1] = PWRSTS_OFF_RET, /* per_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [2] = PWRSTS_OFF_RET, /* ram_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [0] = PWRSTS_ON, /* pruss_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [1] = PWRSTS_ON, /* per_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [2] = PWRSTS_ON, /* ram_mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct powerdomain mpu_33xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "mpu_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .voltdm = { .name = "mpu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .prcm_offs = AM33XX_PRM_MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .pwrsts = PWRSTS_OFF_RET_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .pwrsts_logic_ret = PWRSTS_OFF_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mem_on_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mem_ret_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mem_pwrst_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .mem_retst_mask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .pwrsts_mem_ret = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [0] = PWRSTS_OFF_RET, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [1] = PWRSTS_OFF_RET, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [2] = PWRSTS_OFF_RET, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .pwrsts_mem_on = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [0] = PWRSTS_ON, /* mpu_l1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [1] = PWRSTS_ON, /* mpu_l2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [2] = PWRSTS_ON, /* mpu_ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct powerdomain cefuse_33xx_pwrdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "cefuse_pwrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .voltdm = { .name = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .prcm_offs = AM33XX_PRM_CEFUSE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .pwrsts = PWRSTS_OFF_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct powerdomain *powerdomains_am33xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &gfx_33xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) &rtc_33xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) &wkup_33xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) &per_33xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &mpu_33xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) &cefuse_33xx_pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __init am33xx_powerdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pwrdm_register_pwrdms(powerdomains_am33xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pwrdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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