^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3/4 powerdomain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * XXX This should be moved to the mach-omap2/ directory at the earliest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * opportunity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Powerdomain basic power states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PWRDM_POWER_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PWRDM_POWER_RET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWRDM_POWER_INACTIVE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PWRDM_POWER_ON 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWRDM_MAX_PWRSTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Powerdomain allowable state bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWRSTS_ON (1 << PWRDM_POWER_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PWRSTS_RET (1 << PWRDM_POWER_RET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Powerdomain flags (struct powerdomain.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * bank 1 position. This is true for OMAP3430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * to a lower sleep state without waking up the powerdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PWRDM_HAS_HDWR_SAR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PWRDM_HAS_MPU_QUIRK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Number of memory banks that are power-controllable. On OMAP4430, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * maximum is 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PWRDM_MAX_MEM_BANKS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Maximum number of clockdomains that can be associated with a powerdomain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * PER powerdomain on AM33XX is the worst case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PWRDM_MAX_CLKDMS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* XXX A completely arbitrary number. What is reasonable here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PWRDM_TRANSITION_BAILOUT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clockdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct powerdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct voltagedomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * struct powerdomain - OMAP powerdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @name: Powerdomain name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @voltdm: voltagedomain containing this powerdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @prcm_offs: the address offset from CM_BASE/PRM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @pwrsts: Possible powerdomain power states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @flags: Powerdomain flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @banks: Number of software-controllable memory banks in this powerdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @pwrdm_clkdms: Clockdomains in this powerdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @node: list_head linking all powerdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @voltdm_node: list_head linking all powerdomains in a voltagedomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * in @pwrstctrl_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * in @pwrstctrl_offs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @state_counter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @timer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @state_timer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @_lock_flags: stored flags when @_lock is taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct powerdomain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct voltagedomain *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } voltdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const s16 prcm_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const u8 pwrsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const u8 pwrsts_logic_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const u8 banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const u8 prcm_partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct list_head voltdm_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned state_counter[PWRDM_MAX_PWRSTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned ret_logic_off_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spinlock_t _lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long _lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const u8 pwrstctrl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const u8 pwrstst_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const u32 logicretstate_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_PM_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) s64 timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) s64 state_timer[PWRDM_MAX_PWRSTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * struct pwrdm_ops - Arch specific function implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @pwrdm_set_next_pwrst: Set the target power state for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @pwrdm_read_next_pwrst: Read the target power state set for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @pwrdm_read_pwrst: Read the current power state of a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @pwrdm_wait_transition: Wait for a pd state transition to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @pwrdm_has_voltdm: Check if a voltdm association is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * chips, a powerdomain's power state is not allowed to directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * transition from one low-power state (e.g., CSWR) to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * low-power state (e.g., OFF) without first waking up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * powerdomain. This wastes energy. So OMAP4 chips support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * ability to transition a powerdomain power state directly from one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * low-power state to another. The function pointed to by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * hardware powerdomain state machine to enable this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pwrdm_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int (*pwrdm_has_voltdm)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void (*pwrdm_save_context)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void (*pwrdm_restore_context)(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int pwrdm_complete_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct powerdomain *pwrdm_lookup(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void *user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void *user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool is_logic_state, u8 req_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int pwrdm_read_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int pwrdm_state_switch(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int pwrdm_pre_transition(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int pwrdm_post_transition(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) extern void omap242x_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) extern void omap243x_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) extern void omap3xxx_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) extern void am33xx_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) extern void omap44xx_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) extern void omap54xx_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) extern void dra7xx_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void am43xx_powerdomains_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) extern struct pwrdm_ops omap2_pwrdm_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) extern struct pwrdm_ops omap3_pwrdm_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) extern struct pwrdm_ops am33xx_pwrdm_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) extern struct pwrdm_ops omap4_pwrdm_operations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Common Internal functions used across OMAP rev's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) extern struct powerdomain wkup_omap2_pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) extern struct powerdomain gfx_omap2_pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) extern void pwrdm_lock(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) extern void pwrdm_unlock(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) extern void pwrdms_save_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern void pwrdms_restore_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) extern void pwrdms_lost_power(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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