^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Common powerdomain framework functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "prm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prm-regbits-44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OMAP3 and OMAP4 specific register bit initialisations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Notice that the names here are not according to each power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * domain but the bit mapping used applies to all of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* OMAP3 and OMAP4 Memory Status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Common Internal functions used across OMAP rev's*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) switch (bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return OMAP_MEM0_ONSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return OMAP_MEM1_ONSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return OMAP_MEM2_ONSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return OMAP_MEM3_ONSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return OMAP_MEM4_ONSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) WARN_ON(1); /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) switch (bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return OMAP_MEM0_RETSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return OMAP_MEM1_RETSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return OMAP_MEM2_RETSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return OMAP_MEM3_RETSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return OMAP_MEM4_RETSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) WARN_ON(1); /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return OMAP_MEM0_STATEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return OMAP_MEM1_STATEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return OMAP_MEM2_STATEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return OMAP_MEM3_STATEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return OMAP_MEM4_STATEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) WARN_ON(1); /* should never happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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