Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP4+ Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010-2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Rajendra Nayak <rnayak@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) u16 pm44xx_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct power_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct powerdomain *pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 next_logic_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 saved_logic_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * struct static_dep_map - Static dependency map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @from:	from clockdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @to:		to clockdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct static_dep_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	const char *from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	const char *to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static u32 cpu_suspend_state = PWRDM_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static LIST_HEAD(pwrst_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int omap4_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 cpu_id = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* Save current powerdomain state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* Set targeted power domain states by suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * For MPUSS to hit power domain retention(CSWR or OSWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * since CPU power domain CSWR is not supported by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * Only master CPU follows suspend path. All other CPUs follow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * domain CSWR is not supported by hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	omap4_enter_lowpower(cpu_id, cpu_suspend_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* Restore next powerdomain state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		if (state > pwrst->next_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			pr_info("Powerdomain (%s) didn't enter target state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				pwrst->pwrdm->name, pwrst->next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		pr_crit("Could not enter target state in pm_suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * OMAP4 chip PM currently works only with certain (newer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * versions of bootloaders. This is due to missing code in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 * kernel to properly reset and initialize some devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		 * Warn the user about the bootloader version being one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		 * possible causes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		 * http://www.spinics.net/lists/arm-kernel/msg218641.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		pr_info("Successfully put all powerdomains to target state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define omap4_pm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif /* CONFIG_SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (!pwrdm->pwrsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * through hotplug path and CPU0 explicitly programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * further down in the code path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (!strncmp(pwrdm->name, "cpu", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			cpu_suspend_state = PWRDM_POWER_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (!strncmp(pwrdm->name, "core", 4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	    !strncmp(pwrdm->name, "l4per", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (!pwrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	pwrst->pwrdm = pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 						     PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 							   PWRDM_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	list_add(&pwrst->node, &pwrst_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * omap_default_idle - OMAP4 default ilde routine.'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * by secondary CPU with CONFIG_CPU_IDLE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void omap_default_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	omap_do_wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * The dynamic dependency between MPUSS -> MEMIF and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * expected. The hardware recommendation is to enable static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * dependencies for these to avoid system lock ups or random crashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * The L4 wakeup depedency is added to workaround the OCP sync hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * BUG with 32K synctimer which lead to incorrect timer value read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * are part of L4 wakeup clockdomain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct static_dep_map omap4_static_dep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{.from = "mpuss_clkdm", .to = "l3_emif_clkdm"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{.from = "mpuss_clkdm", .to = "l3_1_clkdm"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{.from = "mpuss_clkdm", .to = "l3_2_clkdm"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{.from = "ducati_clkdm", .to = "l3_1_clkdm"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{.from = "ducati_clkdm", .to = "l3_2_clkdm"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{.from  = NULL} /* TERMINATION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct static_dep_map omap5_dra7_static_dep_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{.from = "mpu_clkdm", .to = "emif_clkdm"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{.from  = NULL} /* TERMINATION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * omap4plus_init_static_deps() - Initialize a static dependency map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * @map:	Mapping of clock domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct clockdomain *from, *to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	while (map->from) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		from = clkdm_lookup(map->from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		to = clkdm_lookup(map->to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (!from || !to) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			pr_err("Failed lookup %s or %s for wakeup dependency\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			       map->from, map->to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ret = clkdm_add_wkdep(from, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			pr_err("Failed to add %s -> %s wakeup dependency(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			       map->from, map->to, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * Initializes basic stuff for power management functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int __init omap4_pm_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (cpu_is_omap446x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (soc_is_omap54xx() || soc_is_dra7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * omap4_pm_init - Init routine for OMAP4+ devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * Initializes all powerdomain and clockdomain target states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * and all PRCM settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * Return: Returns the error code returned by called functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int __init omap4_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (omap_rev() == OMAP4430_REV_ES1_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	pr_info("Power Management for TI OMAP4+ devices.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * OMAP4 chip PM currently works only with certain (newer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * versions of bootloaders. This is due to missing code in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * kernel to properly reset and initialize some devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * http://www.spinics.net/lists/arm-kernel/msg218641.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = pwrdm_for_each(pwrdms_setup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		pr_err("Failed to setup powerdomains.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		ret = omap4plus_init_static_deps(omap4_static_dep_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	else if (soc_is_omap54xx() || soc_is_dra7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		ret = omap4plus_init_static_deps(omap5_dra7_static_dep_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		pr_err("Failed to initialise static dependencies.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = omap4_mpuss_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		pr_err("Failed to initialise OMAP4 MPUSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	omap_common_suspend_init(omap4_pm_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/* Overwrite the default cpu_do_idle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	arm_pm_idle = omap_default_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (cpu_is_omap44xx() || soc_is_omap54xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		omap4_idle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }