^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP3 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jouni Hogander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2007 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Rajendra Nayak <rnayak@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2005 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Based on pm.c for omap1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/omap-gpmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <trace/events/power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/fncpy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "cm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "prm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "prm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "omap-secure.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "vc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* pm34xx errata defined in pm.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 pm34xx_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct power_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct powerdomain *pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static LIST_HEAD(pwrst_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void (*omap3_do_wfi_sram)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct powerdomain *core_pwrdm, *per_pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void omap3_core_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) omap3_ctrl_save_padconf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Force write last pad into memory, as this can fail in some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * cases according to errata 1.157, 1.185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Save the Interrupt controller context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) omap_intc_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Save the GPMC context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) omap3_gpmc_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Save the system control module context, padconf already save above*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) omap3_control_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void omap3_core_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Restore the control module context, padconf restored by h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) omap3_control_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Restore the GPMC context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) omap3_gpmc_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Restore the interrupt controller context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) omap_intc_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * FIXME: This function should be called before entering off-mode after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * OMAP3 secure services have been accessed. Currently it is only called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * once during boot sequence, but this works as we are not using secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * services.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void omap3_save_secure_ram_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * MPU next state must be set to POWER_ON temporarily,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * otherwise the WFI executed inside the ROM code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * will hang the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = omap3_save_secure_ram(omap3_secure_ram_storage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OMAP3_SAVE_SECURE_RAM_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Following is for error tracking, it should not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_err("save_secure_sram() returns %08x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OMAP3430_ST_IO_CHAIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return c ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * these are handled in a separate handler to avoid acking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * IO events before parsing in mux code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) OMAP3430_ST_IO_CHAIN_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (omap_rev() > OMAP3430_REV_ES1_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return c ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void omap34xx_save_context(u32 *save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Read Auxiliary Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *save++ = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *save++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Read L2 AUX ctrl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *save++ = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *save++ = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int omap34xx_do_sram_idle(unsigned long save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) omap34xx_cpu_suspend(save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void omap_sram_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Variable to tell what needs to be saved and restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * in omap_sram_idle*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* save_state = 0 => Nothing to save and restored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* save_state = 1 => Only L1 and logic lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* save_state = 2 => Only L2 lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* save_state = 3 => L1, L2 and logic lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int save_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int mpu_next_state = PWRDM_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int per_next_state = PWRDM_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int core_next_state = PWRDM_POWER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 sdrc_pwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) switch (mpu_next_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case PWRDM_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case PWRDM_POWER_RET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* No need to save context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) save_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case PWRDM_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) save_state = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Invalid state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pr_err("Invalid mpu state in sram_idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* NEON control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Enable IO-PAD and IO-CHAIN wakeups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pwrdm_pre_transition(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (per_next_state == PWRDM_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) error = cpu_cluster_pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (core_next_state < PWRDM_POWER_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (core_next_state == PWRDM_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) omap3_core_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) omap3_cm_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Configure PMIC signaling for I2C4 or sys_off_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) omap3_vc_set_pmic_signaling(core_next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) omap3_intc_prepare_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * On EMU/HS devices ROM code restores a SRDC value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * from scratchpad which has automatic self refresh on timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Hence store/restore the SDRC_POWER register here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) core_next_state == PWRDM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sdrc_pwr = sdrc_read_reg(SDRC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * omap3_arm_context is the location where some ARM context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * get saved. The rest is placed on the stack, and restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * from there before resuming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) omap34xx_save_context(omap3_arm_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (save_state == 1 || save_state == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cpu_suspend(save_state, omap34xx_do_sram_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) omap34xx_do_sram_idle(save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Restore normal SDRC POWER settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) core_next_state == PWRDM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sdrc_write_reg(sdrc_pwr, SDRC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (core_next_state < PWRDM_POWER_ON &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) omap3_core_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) omap3_cm_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) omap3_sram_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) omap2_sms_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * In off-mode resume path above, omap3_core_restore_context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * also handles the INTC autoidle restore done here so limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * this to non-off mode resume paths so we don't do it twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) omap3_intc_resume_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pwrdm_post_transition(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (per_next_state == PWRDM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cpu_cluster_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void omap3_pm_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (omap_irq_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) omap_sram_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int omap3_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int state, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Read current next_pwrsts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) list_for_each_entry(pwrst, &pwrst_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Set ones wanted by suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) omap3_intc_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) omap_sram_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Restore next_pwrsts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (state > pwrst->next_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_info("Powerdomain (%s) didn't enter target state %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pwrst->pwrdm->name, pwrst->next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pr_err("Could not enter target state in pm_suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pr_info("Successfully put all powerdomains to target state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define omap3_pm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif /* CONFIG_SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void __init prcm_setup_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) omap3_ctrl_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) void omap3_pm_off_mode_enable(int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) state = PWRDM_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) state = PWRDM_POWER_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pwrst->pwrdm == core_pwrdm &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) state == PWRDM_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pwrst->next_state = PWRDM_POWER_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pr_warn("%s: Core OFF disabled due to errata i583\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pwrst->next_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (pwrst->pwrdm == pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return pwrst->next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) list_for_each_entry(pwrst, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (pwrst->pwrdm == pwrdm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pwrst->next_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct power_state *pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!pwrdm->pwrsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!pwrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pwrst->pwrdm = pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (enable_off_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pwrst->next_state = PWRDM_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pwrst->next_state = PWRDM_POWER_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) list_add(&pwrst->node, &pwrst_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (pwrdm_has_hdwr_sar(pwrdm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pwrdm_enable_hdwr_sar(pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Push functions to SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * The minimum set of functions is pushed to SRAM for execution:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * - omap3_do_wfi for erratum i581 WA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void omap_push_sram_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void __init pm_errata_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (cpu_is_omap3630()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pm34xx_errata |= PM_RTA_ERRATUM_i608;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Enable the l2 cache toggling in sleep logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) enable_omap3630_toggle_l2_on_restore();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (omap_rev() < OMAP3630_REV_ES1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PM_PER_MEMORIES_ERRATUM_i582);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void __init omap3_pm_check_pmic(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) enable_off_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) enable_off_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int __init omap3_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct power_state *pwrst, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!omap3_has_io_chain_ctrl())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pm_errata_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* XXX prcm_setup_regs needs to be before enabling hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * supervised mode for powerdomains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) prcm_setup_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = request_irq(omap_prcm_event_to_irq("wkup"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pr_err("pm: Failed to request pm_wkup irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* IO interrupt is shared with mux code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = request_irq(omap_prcm_event_to_irq("io"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) omap3_pm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pr_err("pm: Failed to request pm_io irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) omap3_pm_check_pmic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = pwrdm_for_each(pwrdms_setup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pr_err("Failed to setup powerdomains\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (mpu_pwrdm == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pr_err("Failed to get mpu_pwrdm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) neon_pwrdm = pwrdm_lookup("neon_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) per_pwrdm = pwrdm_lookup("per_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) core_pwrdm = pwrdm_lookup("core_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) neon_clkdm = clkdm_lookup("neon_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mpu_clkdm = clkdm_lookup("mpu_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) per_clkdm = clkdm_lookup("per_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) wkup_clkdm = clkdm_lookup("wkup_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) omap_common_suspend_init(omap3_pm_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) arm_pm_idle = omap3_pm_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) omap3_idle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * RTA is disabled during initialization as per erratum i608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * it is safer to disable RTA by the bootloader, but we would like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * to be doubly sure here and prevent any mishaps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) omap3630_ctrl_disable_rta();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * not correctly reset when the PER powerdomain comes back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * from OFF or OSWR when the CORE powerdomain is kept active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * See OMAP36xx Erratum i582 "PER Domain reset issue after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * complete workaround. The kernel must also prevent the PER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * powerdomain from going to OSWR/OFF while the CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * powerdomain is not going to OSWR/OFF. And if PER last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * power state was off while CORE last power state was ON, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * UART3/4 and McBSP2/3 SIDETONE devices need to run a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * self-test using their loopback tests; if that fails, those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * devices are unusable until the PER/CORE can complete a transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * from ON to OSWR/OFF and then back to ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * XXX Technically this workaround is only needed if off-mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * or OSWR is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) clkdm_add_wkdep(per_clkdm, wkup_clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) omap3_secure_ram_storage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!omap3_secure_ram_storage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pr_err("Memory allocation failed when allocating for secure sram context\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) omap3_save_secure_ram_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) omap3_save_scratchpad_contents();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) list_del(&pwrst->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) kfree(pwrst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) free_irq(omap_prcm_event_to_irq("wkup"), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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