^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006-2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Tony Lindgren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Juha Yrjola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Amit Kucheria <amit.kucheria@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Igor Stoppa <igor.stoppa@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Based on pm.c for omap1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/fncpy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/system_misc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "prm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "prm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "cm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "cm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *sdrc_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct powerdomain *mpu_pwrdm, *core_pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct clk *osc_ck, *emul_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int omap2_enter_full_retention(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* There is 1 reference hold for all children of the oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * clock, the following will remove it. If no one else uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * oscillator itself it will be disabled if/when we enter retention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_disable(osc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Clear old wake-up events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* REVISIT: These write to reserved bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Workaround to kill USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* One last check for pending IRQs to avoid extra latency due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * to sleeping unnecessarily. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (omap_irq_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto no_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Jump to SRAM suspend code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) OMAP_SDRC_REGADDR(SDRC_POWER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) no_sleep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clk_enable(osc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* clear CORE wake-up events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* MPU domain wake events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int sti_console_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int omap2_allow_mpu_retention(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!omap2xxx_cm_mpu_retention_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (sti_console_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void omap2_enter_mpu_retention(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const int zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* The peripherals seem not to be able to wake up the MPU when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * it is in retention mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (omap2_allow_mpu_retention()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* REVISIT: These write to reserved bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Try to enter MPU retention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Block MPU retention */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* WFI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int omap2_can_sleep(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (omap2xxx_cm_fclks_active())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (__clk_is_enabled(osc_ck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void omap2_pm_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (omap_irq_pending())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) error = cpu_cluster_pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (error || !omap2_can_sleep()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) omap2_enter_mpu_retention();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto out_cpu_cluster_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) omap2_enter_full_retention();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) out_cpu_cluster_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cpu_cluster_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void __init prcm_setup_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i, num_mem_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct powerdomain *pwrdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Enable autoidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * XXX This should be handled by hwmod code or PRCM init code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) OMAP2_PRCM_SYSCONFIG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Set CORE powerdomain memory banks to retain their contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * during RETENTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (i = 0; i < num_mem_banks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Force-power down DSP, GFX powerdomains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pwrdm = clkdm_get_pwrdm(dsp_clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pwrdm = clkdm_get_pwrdm(gfx_clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Enable hardware-supervised idle for all clkdms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clkdm_for_each(omap_pm_clkdms_setup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) omap_common_suspend_init(omap2_enter_full_retention);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * stabilisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) OMAP2_PRCM_CLKSSETUP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Configure automatic voltage transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) OMAP2_PRCM_VOLTSETUP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) OMAP24XX_MEMRETCTRL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Enable wake-up events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) WKUP_MOD, PM_WKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Enable SYS_CLKEN control when all domains idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int __init omap2_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) printk(KERN_INFO "Power Management for OMAP2 initializing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Look up important powerdomains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!mpu_pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pr_err("PM: mpu_pwrdm not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) core_pwrdm = pwrdm_lookup("core_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!core_pwrdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_err("PM: core_pwrdm not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Look up important clockdomains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mpu_clkdm = clkdm_lookup("mpu_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!mpu_clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pr_err("PM: mpu_clkdm not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wkup_clkdm = clkdm_lookup("wkup_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!wkup_clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_err("PM: wkup_clkdm not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dsp_clkdm = clkdm_lookup("dsp_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!dsp_clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_err("PM: dsp_clkdm not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) gfx_clkdm = clkdm_lookup("gfx_clkdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!gfx_clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pr_err("PM: gfx_clkdm not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) osc_ck = clk_get(NULL, "osc_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (IS_ERR(osc_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) printk(KERN_ERR "could not get osc_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (cpu_is_omap242x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) emul_ck = clk_get(NULL, "emul_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (IS_ERR(emul_ck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) printk(KERN_ERR "could not get emul_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) clk_put(osc_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) prcm_setup_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * We copy the assembler sleep/wakeup routines to SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * These routines need to be in SRAM as that's the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * memory the MPU can see when it wakes up after the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * chip enters idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) omap24xx_cpu_suspend_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) arm_pm_idle = omap2_pm_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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