^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jouni Hogander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __ARCH_ARM_MACH_OMAP2_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_CPU_IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern int __init omap3_idle_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern int __init omap4_idle_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static inline int omap3_idle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static inline int omap4_idle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern void *omap3_secure_ram_storage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern void omap3_pm_off_mode_enable(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) extern void omap_sram_idle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #if defined(CONFIG_PM_OPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern int omap3_opp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern int omap4_opp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline int omap3_opp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline int omap4_opp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern u32 enable_off_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define pm_dbg_update_time(pwrdm, prev) do {} while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif /* CONFIG_PM_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* 24xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern void omap24xx_idle_loop_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) extern unsigned int omap24xx_idle_loop_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *sdrc_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern unsigned int omap24xx_cpu_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* 3xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void omap34xx_cpu_suspend(int save_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* omap3_do_wfi function pointer and size, for copy to SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern void omap3_do_wfi(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern unsigned int omap3_do_wfi_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ... and its pointer from SRAM after copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern void (*omap3_do_wfi_sram)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern struct am33xx_pm_sram_addr am33xx_pm_sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern struct am33xx_pm_sram_addr am43xx_pm_sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern void omap3_save_scratchpad_contents(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PM_RTA_ERRATUM_i608 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern u16 pm34xx_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern void enable_omap3630_toggle_l2_on_restore(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IS_PM34XX_ERRATUM(id) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void enable_omap3630_toggle_l2_on_restore(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) ||\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern u16 pm44xx_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IS_PM44XX_ERRATUM(id) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP4_VP_CONFIG_ERROROFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_POWER_AVS_OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern int omap_devinit_smartreflex(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) extern void omap_enable_smartreflex_on_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline int omap_devinit_smartreflex(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void omap_enable_smartreflex_on_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_TWL4030_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern int omap3_twl_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern int omap4_twl_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern int omap3_twl_set_sr_bit(bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline int omap3_twl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline int omap4_twl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #if IS_ENABLED(CONFIG_MFD_CPCAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern int omap4_cpcap_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline int omap4_cpcap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void omap_common_suspend_init(void *pm_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline void omap_common_suspend_init(void *pm_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif /* CONFIG_SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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