Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * TI AM33XX and AM43XX PM Assembly Offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017-2018 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/kbuild.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/platform_data/pm33xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ti-emif-sram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) int main(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	ti_emif_asm_offsets();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	DEFINE(AMX3_PM_WFI_FLAGS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	       offsetof(struct am33xx_pm_sram_data, wfi_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	DEFINE(AMX3_PM_L2_AUX_CTRL_VAL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	       offsetof(struct am33xx_pm_sram_data, l2_aux_ctrl_val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	DEFINE(AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	       offsetof(struct am33xx_pm_sram_data, l2_prefetch_ctrl_val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	DEFINE(AMX3_PM_SRAM_DATA_SIZE, sizeof(struct am33xx_pm_sram_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	DEFINE(AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	       offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_virt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	DEFINE(AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	       offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	DEFINE(AMX3_PM_RTC_BASE_VIRT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	       offsetof(struct am33xx_pm_ro_sram_data, rtc_base_virt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	DEFINE(AMX3_PM_RO_SRAM_DATA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	       sizeof(struct am33xx_pm_ro_sram_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }