^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * These configurations are characterized by voltage and speed for clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The device is only validated for certain combinations. One way to express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * these combinations is via the 'ratio's' which the clocks operate with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * respect to each other. These ratio sets are for a given voltage/DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * setting. All configurations can be described by a DPLL setting and a ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 2430 differs from 2420 in that there are no more phase synchronizers used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 2430 (iva2.1, NOdsp, mdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * XXX Missing voltage data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * THe format described in this file is deprecated. Once a reasonable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OPP API exists, the data in this file should be converted to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * This is technically part of the OMAP2xxx clock code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * struct prcm_config - define clock rates on a per-OPP basis (24xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This is deprecated. As soon as we have a decent OPP API, we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * move all this stuff to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct prcm_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long xtal_speed; /* crystal rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long mpu_speed; /* speed of MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long cm_clksel_mpu; /* mpu divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long cm_clksel_gfx; /* gfx dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long cm_clksel1_core; /* major subsystem dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long cm_clksel1_pll; /* m,n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long base_sdrc_rfr; /* base refresh timing for a set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned short flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Core fields for cm_clksel, not ratio governed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RX_CLKSEL_DSS1 (0x10 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RX_CLKSEL_DSS2 (0x0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RX_CLKSEL_SSI (0x5 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Voltage/DPLL ratios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* 2430 Ratio's, 2430-Ratio Config 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R1_CLKSEL_L3 (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R1_CLKSEL_L4 (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R1_CLKSEL_USB (4 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) R1_CLKSEL_L4 | R1_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R1_CLKSEL_MPU (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define R1_CLKSEL_DSP (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R1_CLKSEL_DSP_IF (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R1_CLKSEL_GFX (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R1_CLKSEL_MDM (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 2430-Ratio Config 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R2_CLKSEL_L3 (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define R2_CLKSEL_L4 (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define R2_CLKSEL_USB (2 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) R2_CLKSEL_L4 | R2_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R2_CLKSEL_MPU (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R2_CLKSEL_DSP (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R2_CLKSEL_DSP_IF (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R2_CLKSEL_GFX (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R2_CLKSEL_MDM (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 2430-Ratio Bootm (BYPASS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RB_CLKSEL_L3 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RB_CLKSEL_L4 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RB_CLKSEL_USB (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RB_CLKSEL_L4 | RB_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RB_CLKSEL_MPU (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RB_CLKSEL_DSP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RB_CLKSEL_DSP_IF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RB_CLKSEL_GFX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RB_CLKSEL_MDM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 2420 Ratio Equivalents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RXX_CLKSEL_VLYNQ (0x12 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RXX_CLKSEL_SSI (0x8 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 2420-PRCM III 532MHz core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RIII_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) RIII_CLKSEL_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* 2420-PRCM II 600MHz core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) RII_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) RII_CLKSEL_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 2420-PRCM I 660MHz core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RI_CLKSEL_L4 | RI_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RI_SYNC_DSP (1 << 7) /* Activate sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RI_SYNC_IVA (0 << 13) /* Bypass sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) RI_CLKSEL_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* 2420-PRCM VII (boot) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RVII_CLKSEL_L3 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RVII_CLKSEL_L4 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RVII_CLKSEL_DSS1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RVII_CLKSEL_DSS2 (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RVII_CLKSEL_VLYNQ (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RVII_CLKSEL_SSI (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RVII_CLKSEL_USB (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RVII_CLKSEL_VLYNQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RVII_CLKSEL_DSP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RVII_CLKSEL_DSP_IF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RVII_SYNC_DSP (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RVII_CLKSEL_IVA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RVII_SYNC_IVA (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) RVII_CLKSEL_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RVII_CLKSEL_GFX (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*-------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 2430 Target modes: Along with each configuration the CPU has several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * modes which goes along with them. Modes mainly are the addition of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * describe DPLL combinations to go along with a ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Hardware governed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MX_48M_SRC (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MX_54M_SRC (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MX_APLLS_CLIKIN_12 (3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MX_APLLS_CLIKIN_13 (2 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MX_APLLS_CLIKIN_19_2 (0 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define M5A_DPLL_MULT_12 (133 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define M5A_DPLL_DIV_12 (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define M5A_DPLL_MULT_13 (61 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define M5A_DPLL_DIV_13 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define M5A_DPLL_MULT_19 (55 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define M5A_DPLL_DIV_19 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MX_APLLS_CLIKIN_19_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define M5B_DPLL_MULT_12 (50 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define M5B_DPLL_DIV_12 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define M5B_DPLL_MULT_13 (200 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define M5B_DPLL_DIV_13 (12 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define M5B_DPLL_MULT_19 (125 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define M5B_DPLL_DIV_19 (31 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MX_APLLS_CLIKIN_19_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define M4_DPLL_MULT_12 (133 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define M4_DPLL_DIV_12 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define M4_DPLL_MULT_13 (399 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define M4_DPLL_DIV_13 (12 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define M4_DPLL_MULT_19 (145 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define M4_DPLL_DIV_19 (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MX_APLLS_CLIKIN_19_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define M3_DPLL_MULT_12 (55 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define M3_DPLL_DIV_12 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define M3_DPLL_MULT_13 (76 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define M3_DPLL_DIV_13 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define M3_DPLL_MULT_19 (17 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define M3_DPLL_DIV_19 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MX_APLLS_CLIKIN_19_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define M2_DPLL_MULT_12 (55 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define M2_DPLL_DIV_12 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * relock time issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Core frequency changed from 330/165 to 329/164 MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define M2_DPLL_MULT_13 (76 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define M2_DPLL_DIV_13 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define M2_DPLL_MULT_19 (17 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define M2_DPLL_DIV_19 (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MX_APLLS_CLIKIN_19_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* boot (boot) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MB_DPLL_MULT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MB_DPLL_DIV (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MB_DPLL_DIV | MB_DPLL_MULT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MB_DPLL_DIV | MB_DPLL_MULT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MB_DPLL_DIV | MB_DPLL_MULT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MX_APLLS_CLIKIN_19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * 2430 - chassis (sedna)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * 165 (ratio1) same as above #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * 150 (ratio1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * 133 (ratio2) same as above #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * 110 (ratio2) same as above #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * 104 (ratio2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * boot (boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* PRCM I target DPLL = 2*330MHz = 660MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MI_DPLL_MULT_12 (55 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MI_DPLL_DIV_12 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * 2420 Equivalent - mode registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * PRCM II , target DPLL = 2*300MHz = 600MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MII_DPLL_MULT_12 (50 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MII_DPLL_DIV_12 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MII_DPLL_MULT_13 (300 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MII_DPLL_DIV_13 (12 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* PRCM III target DPLL = 2*266 = 532MHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MIII_DPLL_MULT_12 (133 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MIII_DPLL_DIV_12 (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MIII_DPLL_DIV_12 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MIII_DPLL_MULT_13 (266 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MIII_DPLL_DIV_13 (12 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MIII_DPLL_DIV_13 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* PRCM VII (boot bypass) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* High and low operation value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* MPU speed defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define S12M 12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define S13M 13000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define S19M 19200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define S26M 26000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define S100M 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define S133M 133000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define S150M 150000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define S164M 164000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define S165M 165000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define S199M 199000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define S200M 200000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define S266M 266000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define S300M 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define S329M 329000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define S330M 330000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define S399M 399000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define S400M 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define S532M 532000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define S600M 600000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define S658M 658000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define S660M 660000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define S798M 798000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) extern const struct prcm_config omap2420_rate_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef CONFIG_SOC_OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) extern const struct prcm_config omap2430_rate_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define omap2430_rate_table NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) extern const struct prcm_config *rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) extern const struct prcm_config *curr_prcm_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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