^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * opp2430_data.c - old-style "OPP" table for OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * These configurations are characterized by voltage and speed for clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The device is only validated for certain combinations. One way to express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * these combinations is via the 'ratios' which the clocks operate with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * respect to each other. These ratio sets are for a given voltage/DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * setting. All configurations can be described by a DPLL setting and a ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 2430 differs from 2420 in that there are no more phase synchronizers used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 2430 (iva2.1, NOdsp, mdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * XXX Missing voltage data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * XXX Missing 19.2MHz sys_clk rate sets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * THe format described in this file is deprecated. Once a reasonable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OPP API exists, the data in this file should be converted to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * This is technically part of the OMAP2xxx clock code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "opp2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Filling in table based on 2430-SDPs variants available. There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * quite a few more rate combinations which could be defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * When multiple values are defined the start up will try and choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * the fastest one. If a 'fast' value is defined, then automatically,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * the /2 one should be included as it can be used. Generally having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * more than one fast set does not make sense, as static timings need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * to be changed to change the set. The exception is the bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * setting which is available for low power bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Note: This table needs to be sorted, fastest to slowest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct prcm_config omap2430_rate_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PRCM #4 - ratio2 (ES2.1) - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PRCM #2 - ratio1 (ES2) - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SDRC_RFR_CTRL_165MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* PRCM #5a - ratio1 - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* PRCM #5b - ratio1 - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SDRC_RFR_CTRL_100MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* PRCM #4 - ratio1 (ES2.1) - SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PRCM #2 - ratio1 (ES2) - SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SDRC_RFR_CTRL_165MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PRCM #5a - ratio1 - SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* PRCM #5b - ratio1 - SLOW*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SDRC_RFR_CTRL_100MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* PRCM-boot/bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SDRC_RFR_CTRL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* PRCM-boot/bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SDRC_RFR_CTRL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RATE_IN_243X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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