^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * opp2420_data.c - old-style "OPP" table for OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * These configurations are characterized by voltage and speed for clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The device is only validated for certain combinations. One way to express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * these combinations is via the 'ratios' which the clocks operate with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * respect to each other. These ratio sets are for a given voltage/DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * setting. All configurations can be described by a DPLL setting and a ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * XXX Missing voltage data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * THe format described in this file is deprecated. Once a reasonable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OPP API exists, the data in this file should be converted to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * This is technically part of the OMAP2xxx clock code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Considerable work is still needed to fully support dynamic frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * changes on OMAP2xxx-series chips. Readers interested in such a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * project are encouraged to review the Maemo Diablo RX-34 and RX-44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * kernel source at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "opp2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Filling in table based on H4 boards available. There are quite a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * few more rate combinations which could be defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * When multiple values are defined the start up will try and choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * the fastest one. If a 'fast' value is defined, then automatically,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the /2 one should be included as it can be used. Generally having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * more than one fast set does not make sense, as static timings need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * to be changed to change the set. The exception is the bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * setting which is available for low power bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Note: This table needs to be sorted, fastest to slowest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct prcm_config omap2420_rate_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* PRCM I - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* PRCM II - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* PRCM III - FAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* PRCM II - SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PRCM III - SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* PRCM-VII (boot-bypass) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* PRCM-VII (boot-bypass) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RATE_IN_242X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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