Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP and TWL PMIC specific initializations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010 Texas Instruments Incorporated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Thara Gopinath
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2009 Texas Instruments Incorporated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Nishanth Menon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "voltage.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define OMAP3_SRI2C_SLAVE_ADDR		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OMAP3_VDD_MPU_SR_CONTROL_REG	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define OMAP3_VDD_CORE_SR_CONTROL_REG	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define OMAP3_VP_CONFIG_ERROROFFSET	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define OMAP3_VP_VSTEPMIN_VSTEPMIN	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OMAP3_VP_VSTEPMAX_VSTEPMAX	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OMAP3_VP_VLIMITTO_TIMEOUT_US	200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OMAP4_SRI2C_SLAVE_ADDR		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OMAP4_VDD_MPU_SR_VOLT_REG	0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OMAP4_VDD_MPU_SR_CMD_REG	0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OMAP4_VDD_IVA_SR_VOLT_REG	0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OMAP4_VDD_IVA_SR_CMD_REG	0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OMAP4_VDD_CORE_SR_VOLT_REG	0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP4_VDD_CORE_SR_CMD_REG	0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static bool is_offset_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static u8 smps_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REG_SMPS_OFFSET         0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static unsigned long twl4030_vsel_to_uv(const u8 vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	return (((vsel * 125) + 6000)) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static u8 twl4030_uv_to_vsel(unsigned long uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return DIV_ROUND_UP(uv - 600000, 12500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static unsigned long twl6030_vsel_to_uv(const u8 vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * In TWL6030 depending on the value of SMPS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * efuse register the voltage range supported in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * standard mode can be either between 0.6V - 1.3V or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * is programmed to all 0's where as starting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * TWL6030 ES1.1 the efuse is programmed to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (!is_offset_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				REG_SMPS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		is_offset_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (!vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * There is no specific formula for voltage to vsel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * conversion above 1.3V. There are special hardcoded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * values for voltages above 1.3V. Currently we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * hardcoding only for 1.35 V which is used for 1GH OPP for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * OMAP4430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (vsel == 0x3A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return 1350000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (smps_offset & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return ((((vsel - 1) * 1266) + 70900)) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return ((((vsel - 1) * 1266) + 60770)) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static u8 twl6030_uv_to_vsel(unsigned long uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * In TWL6030 depending on the value of SMPS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * efuse register the voltage range supported in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * standard mode can be either between 0.6V - 1.3V or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * is programmed to all 0's where as starting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * TWL6030 ES1.1 the efuse is programmed to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (!is_offset_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				REG_SMPS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		is_offset_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (!uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * There is no specific formula for voltage to vsel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * conversion above 1.3V. There are special hardcoded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * values for voltages above 1.3V. Currently we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * hardcoding only for 1.35 V which is used for 1GH OPP for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * OMAP4430.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (uv > twl6030_vsel_to_uv(0x39)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if (uv == 1350000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			return 0x3A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			__func__, uv, twl6030_vsel_to_uv(0x39));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return 0x3A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (smps_offset & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return DIV_ROUND_UP(uv - 709000, 12660) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return DIV_ROUND_UP(uv - 607700, 12660) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct omap_voltdm_pmic omap3_mpu_pmic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.slew_rate		= 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.step_size		= 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.vddmin			= 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.vddmax			= 1450000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.volt_reg_addr		= OMAP3_VDD_MPU_SR_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.i2c_high_speed		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.vsel_to_uv		= twl4030_vsel_to_uv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.uv_to_vsel		= twl4030_uv_to_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct omap_voltdm_pmic omap3_core_pmic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.slew_rate		= 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.step_size		= 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.vp_erroroffset		= OMAP3_VP_CONFIG_ERROROFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.vp_vstepmin		= OMAP3_VP_VSTEPMIN_VSTEPMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.vp_vstepmax		= OMAP3_VP_VSTEPMAX_VSTEPMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.vddmin			= 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.vddmax			= 1450000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.vp_timeout_us		= OMAP3_VP_VLIMITTO_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.i2c_slave_addr		= OMAP3_SRI2C_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.volt_reg_addr		= OMAP3_VDD_CORE_SR_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.i2c_high_speed		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.vsel_to_uv		= twl4030_vsel_to_uv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.uv_to_vsel		= twl4030_uv_to_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct omap_voltdm_pmic omap4_mpu_pmic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.slew_rate		= 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.step_size		= 12660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.vddmin			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.vddmax			= 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.volt_reg_addr		= OMAP4_VDD_MPU_SR_VOLT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.cmd_reg_addr		= OMAP4_VDD_MPU_SR_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.i2c_high_speed		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.i2c_pad_load		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.vsel_to_uv		= twl6030_vsel_to_uv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.uv_to_vsel		= twl6030_uv_to_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct omap_voltdm_pmic omap4_iva_pmic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.slew_rate		= 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.step_size		= 12660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.vddmin			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.vddmax			= 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.volt_reg_addr		= OMAP4_VDD_IVA_SR_VOLT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.cmd_reg_addr		= OMAP4_VDD_IVA_SR_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.i2c_high_speed		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.i2c_pad_load		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.vsel_to_uv		= twl6030_vsel_to_uv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.uv_to_vsel		= twl6030_uv_to_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct omap_voltdm_pmic omap4_core_pmic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.slew_rate		= 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.step_size		= 12660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.vp_erroroffset		= OMAP4_VP_CONFIG_ERROROFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.vp_vstepmin		= OMAP4_VP_VSTEPMIN_VSTEPMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.vp_vstepmax		= OMAP4_VP_VSTEPMAX_VSTEPMAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.vddmin			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.vddmax			= 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.vp_timeout_us		= OMAP4_VP_VLIMITTO_TIMEOUT_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.i2c_slave_addr		= OMAP4_SRI2C_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.volt_reg_addr		= OMAP4_VDD_CORE_SR_VOLT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.cmd_reg_addr		= OMAP4_VDD_CORE_SR_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.i2c_high_speed		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.i2c_pad_load		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.vsel_to_uv		= twl6030_vsel_to_uv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.uv_to_vsel		= twl6030_uv_to_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int __init omap4_twl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct voltagedomain *voltdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!cpu_is_omap44xx() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	    of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	voltdm = voltdm_lookup("mpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	voltdm = voltdm_lookup("iva");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	voltdm = voltdm_lookup("core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int __init omap3_twl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct voltagedomain *voltdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (!cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	voltdm = voltdm_lookup("mpu_iva");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	voltdm = voltdm_lookup("core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }