^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap_hwmod macros, structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Created in collaboration with (alphabetical order): Benoît Cousson,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * These headers and macros are used to define OMAP on-chip module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * data and their integration with other OMAP modules and Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copious documentation and references can also be found in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * writing).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * To do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - add interconnect error log structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - init_conn_id_bit (CONNID_BIT_VECTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - implement default hwmod SMS/SDRC flags?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - move Linux-specific data ("non-ROM data") out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct omap_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern struct sysc_regbits omap_hwmod_sysc_type1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern struct sysc_regbits omap_hwmod_sysc_type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern struct sysc_regbits omap_hwmod_sysc_type3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern struct sysc_regbits omap34xx_sr_sysc_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern struct sysc_regbits omap36xx_sr_sysc_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern struct sysc_regbits omap3_sham_sysc_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern struct sysc_regbits omap3xxx_aes_sysc_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern struct sysc_regbits omap_hwmod_sysc_type_mcasp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * with the original PRCM protocol defined for OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SYSC_TYPE1_MIDLEMODE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SYSC_TYPE1_SIDLEMODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SYSC_TYPE1_SOFTRESET_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SYSC_TYPE1_AUTOIDLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * with the new PRCM protocol defined for new OMAP4 IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SYSC_TYPE2_SOFTRESET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SYSC_TYPE2_SIDLEMODE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SYSC_TYPE2_MIDLEMODE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SYSC_TYPE2_DMADISABLE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * OCP SYSCONFIG bit shifts/masks TYPE3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * This is applicable for some IPs present in AM33XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SYSC_TYPE3_SIDLEMODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SYSC_TYPE3_MIDLEMODE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* OCP SYSSTATUS bit shifts/masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SYSS_RESETDONE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Master standby/slave idle mode flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HWMOD_IDLEMODE_FORCE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HWMOD_IDLEMODE_NO (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HWMOD_IDLEMODE_SMART (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* modulemode control type (SW or HW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MODULEMODE_HWCTRL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MODULEMODE_SWCTRL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DEBUG_OMAP2UART1_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DEBUG_OMAP2UART2_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DEBUG_OMAP2UART3_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DEBUG_OMAP3UART3_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DEBUG_OMAP3UART4_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DEBUG_OMAP4UART3_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DEBUG_OMAP4UART4_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DEBUG_TI81XXUART1_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DEBUG_TI81XXUART2_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DEBUG_TI81XXUART3_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DEBUG_AM33XXUART1_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_OMAP_GPMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEBUG_OMAP_GPMC_HWMOD_FLAGS HWMOD_INIT_NO_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DEBUG_OMAP_GPMC_HWMOD_FLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #if defined(CONFIG_DEBUG_OMAP2UART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #undef DEBUG_OMAP2UART1_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #elif defined(CONFIG_DEBUG_OMAP2UART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #undef DEBUG_OMAP2UART2_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #elif defined(CONFIG_DEBUG_OMAP2UART3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #undef DEBUG_OMAP2UART3_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #elif defined(CONFIG_DEBUG_OMAP3UART3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #undef DEBUG_OMAP3UART3_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #elif defined(CONFIG_DEBUG_OMAP3UART4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #undef DEBUG_OMAP3UART4_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #elif defined(CONFIG_DEBUG_OMAP4UART3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #undef DEBUG_OMAP4UART3_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #elif defined(CONFIG_DEBUG_OMAP4UART4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #undef DEBUG_OMAP4UART4_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #elif defined(CONFIG_DEBUG_TI81XXUART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #undef DEBUG_TI81XXUART1_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #elif defined(CONFIG_DEBUG_TI81XXUART2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #undef DEBUG_TI81XXUART2_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #elif defined(CONFIG_DEBUG_TI81XXUART3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #undef DEBUG_TI81XXUART3_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #elif defined(CONFIG_DEBUG_AM33XXUART1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #undef DEBUG_AM33XXUART1_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @name: name of the reset line (module local name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @rst_shift: Offset of the reset bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @st_shift: Offset of the reset status bit (OMAP2/3 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @name should be something short, e.g., "cpu0" or "rst". It is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * locally to the hwmod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct omap_hwmod_rst_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 rst_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 st_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @role: "sys", "32k", "tv", etc -- for use in clk_get()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @clk: opt clock: OMAP clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @_clk: pointer to the struct clk (filled in at runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * The module's interface clock and main functional clock should not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * be added as optional clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct omap_hwmod_opt_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const char *role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const char *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk *_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* omap_hwmod_omap2_firewall.flags bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP_FIREWALL_L3 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP_FIREWALL_L4 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @l4_fw_region: L4 firewall region ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @l4_prot_group: L4 protection group ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct omap_hwmod_omap2_firewall {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 l3_perm_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 l4_fw_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 l4_prot_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * interface to interact with the hwmod. Used to add sleep dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * when the module is enabled or disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OCP_USER_MPU (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OCP_USER_SDMA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OCP_USER_DSP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OCP_USER_IVA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* omap_hwmod_ocp_if.flags bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OCPIF_SWSUP_IDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OCPIF_CAN_BURST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* omap_hwmod_ocp_if._int_flags possibilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define _OCPIF_INT_FLAGS_REGISTERED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * struct omap_hwmod_ocp_if - OCP interface data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @master: struct omap_hwmod that initiates OCP transactions on this link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @slave: struct omap_hwmod that responds to OCP transactions on this link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @addr: address space associated with this link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @clk: interface clock: OMAP clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @_clk: pointer to the interface struct clk (filled in at runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @fw: interface firewall data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @width: OCP data width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @user: initiators using this interface (see OCP_USER_* macros above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @flags: OCP interface flags (see OCPIF_* macros above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * It may also be useful to add a tag_cnt field for OCP2.x devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Parameter names beginning with an underscore are managed internally by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * the omap_hwmod code and should not be set during initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct omap_hwmod_ocp_if {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct omap_hwmod *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct omap_hwmod *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct omap_hwmod_addr_space *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const char *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clk *_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct omap_hwmod_omap2_firewall omap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 _int_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Macros for use in struct omap_hwmod_sysconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Flags for use in omap_hwmod_sysconfig.idlemodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MASTER_STANDBY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SLAVE_IDLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* omap_hwmod_sysconfig.sysc_flags capability flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SYSC_HAS_AUTOIDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SYSC_HAS_SOFTRESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SYSC_HAS_ENAWAKEUP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SYSC_HAS_EMUFREE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SYSC_HAS_CLOCKACTIVITY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SYSC_HAS_SIDLEMODE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SYSC_HAS_MIDLEMODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SYSS_HAS_RESET_STATUS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SYSC_HAS_RESET_STATUS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SYSC_HAS_DMADISABLE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* omap_hwmod_sysconfig.clockact flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLOCKACT_TEST_BOTH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLOCKACT_TEST_MAIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLOCKACT_TEST_ICLK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLOCKACT_TEST_NONE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @rev_offs: IP block revision register offset (from module base addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @srst_udelay: Delay needed after doing a softreset in usecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @clockact: the default value of the module CLOCKACTIVITY bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @clockact describes to the module which clocks are likely to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * disabled when the PRCM issues its idle request to the module. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * modules have separate clockdomains for the interface clock and main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * functional clock, and can check whether they should acknowledge the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * idle request based on the internal module functionality that has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * been associated with the clocks marked in @clockact. This field is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @sysc_fields: structure containing the offset positions of various bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * whether the device ip is compliant with the original PRCM protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * If the device follows a different scheme for the sysconfig register ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * then this field has to be populated with the correct offset structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct omap_hwmod_class_sysconfig {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) s32 rev_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) s32 sysc_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) s32 syss_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 sysc_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct sysc_regbits *sysc_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 srst_udelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 idlemodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @module_offs: PRCM submodule offset from the start of the PRM/CM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * WKEN, GRPSEL registers. In an ideal world, no extra information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * would be needed for IDLEST information, but alas, there are some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct omap_hwmod_omap2_prcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) s16 module_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 idlest_reg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 idlest_idle_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Possible values for struct omap_hwmod_omap4_prcm.flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * module-level context loss register associated with them; this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * flag bit should be set in those cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * offset of zero; this flag bit should be set in those cases to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * distinguish from hwmods that have no clkctrl offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * by the common clock framework and not hwmod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * @clkctrl_offs: offset of the PRCM clock control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * @context_offs: offset of the RM_*_CONTEXT register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * @submodule_wkdep_bit: bit shift of the WKDEP range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @flags: PRCM register capabilities for this IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @modulemode: allowable modulemodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @context_lost_counter: Count of module level context lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * If @lostcontext_mask is not defined, context loss check code uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * whole register without masking. @lostcontext_mask should only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * defined in cases where @context_offs register is shared by two or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * more hwmods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct omap_hwmod_omap4_prcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 clkctrl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 rstctrl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u16 rstst_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u16 context_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 lostcontext_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 submodule_wkdep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u8 modulemode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int context_lost_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * omap_hwmod.flags definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * of idle, rather than relying on module smart-idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * out of standby, rather than relying on module smart-standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * XXX Should be HWMOD_SETUP_NO_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * controller, etc. XXX probably belongs outside the main hwmod file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * XXX Should be HWMOD_SETUP_NO_IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * when module is enabled, rather than the default, which is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * enable autoidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * only for few initiator modules on OMAP2 & 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * This is needed for devices like DSS that require optional clocks enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * in order to complete the reset. Optional clocks will be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * again after the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * HWMOD_16BIT_REG: Module has 16bit registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * this IP block comes from an off-chip source and is not always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * enabled. This prevents the hwmod code from being able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * enable and reset the IP block early. XXX Eventually it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * be possible to query the clock framework for this information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * correctly if the MPU is allowed to go idle while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * peripherals are active. This is apparently true for the I2C on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * OMAP2420, and also the EMAC on AM3517/3505. It's unlikely that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * this is really true -- we're probably not configuring something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * correctly, or this is being abused to deal with some PM latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * issues -- but we're currently suffering from a shortage of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * folks who are able to track these issues down properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * is kept in force-standby mode. Failing to do so causes PM problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * with musb on OMAP3630 at least. Note that musb has a dedicated register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * to control MSTANDBY signal when MIDLEMODE is set to force-standby.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * out of idle, but rely on smart-idle to the put it back in idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * so the wakeups are still functional (Only known case for now is UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * events by calling _reconfigure_io_chain() when a device is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * or idled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * operate and they need to be handled at the same time as the main_clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * IPs like CPSW on DRA7, where clocks to this module cannot be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * HWMOD_CLKDM_NOAUTO: Allows the hwmod's clockdomain to be prevented from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * entering HW_AUTO while hwmod is active. This is needed to workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * some modules which don't function correctly with HW_AUTO. For example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * DCAN on DRA7x SoC needs this to workaround errata i893.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define HWMOD_SWSUP_SIDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HWMOD_SWSUP_MSTANDBY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define HWMOD_INIT_NO_RESET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define HWMOD_INIT_NO_IDLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define HWMOD_NO_IDLEST (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define HWMOD_16BIT_REG (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define HWMOD_BLOCK_WFI (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HWMOD_FORCE_MSTANDBY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define HWMOD_SWSUP_SIDLE_ACT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define HWMOD_RECONFIG_IO_CHAIN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HWMOD_OPT_CLKS_NEEDED (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HWMOD_NO_IDLE (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define HWMOD_CLKDM_NOAUTO (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * omap_hwmod._int_flags definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * These are for internal use only and are managed by the omap_hwmod code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * causes the first call to _enable() to only update the pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define _HWMOD_NO_MPU_PORT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define _HWMOD_SYSCONFIG_LOADED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define _HWMOD_SKIP_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * omap_hwmod._state definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * INITIALIZED: reset (optionally), initialized, enabled, disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * (optionally)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define _HWMOD_STATE_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define _HWMOD_STATE_REGISTERED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define _HWMOD_STATE_CLKS_INITED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define _HWMOD_STATE_INITIALIZED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define _HWMOD_STATE_ENABLED 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define _HWMOD_STATE_IDLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define _HWMOD_STATE_DISABLED 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define _HWMOD_STATE_DEFAULT _HWMOD_STATE_IDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define _HWMOD_STATE_DEFAULT _HWMOD_STATE_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * struct omap_hwmod_class - the type of an IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * @name: name of the hwmod_class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * @sysc: device SYSCONFIG/SYSSTATUS register data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @lock: ptr to fn to be executed to lock IP registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @unlock: ptr to fn to be executed to unlock IP registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Represent the class of a OMAP hardware "modules" (e.g. timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * smartreflex, gpio, uart...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @pre_shutdown is a function that will be run immediately before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * hwmod clocks are disabled, etc. It is intended for use for hwmods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * like the MPU watchdog, which cannot be disabled with the standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * omap_hwmod_shutdown(). The function should return 0 upon success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * or some negative error upon failure. Returning an error will cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * omap_hwmod_shutdown() to abort the device shutdown and return an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * If @reset is defined, then the function it points to will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * executed in place of the standard hwmod _reset() code in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * unusual reset sequences - usually processor IP blocks like the IVA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct omap_hwmod_class {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct omap_hwmod_class_sysconfig *sysc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int (*pre_shutdown)(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int (*reset)(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void (*lock)(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void (*unlock)(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @name: name of the hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @class: struct omap_hwmod_class * to the class of this hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @od: struct omap_device currently associated with this hwmod (internal use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * @prcm: PRCM data pertaining to this hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * @main_clk: main clock: OMAP clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @_clk: pointer to the main struct clk (filled in at runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @opt_clks: other device clocks that drivers can request (0..*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * @voltdm: pointer to voltage domain (filled in at runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * @dev_attr: arbitrary device attributes that can be passed to the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * @_sysc_cache: internal-use hwmod flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * @mpu_rt_idx: index of device address space for register target (for DT boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * @_mpu_rt_va: cached register target start address (internal use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * @_mpu_port: cached MPU register target slave (internal use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @opt_clks_cnt: number of @opt_clks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @master_cnt: number of @master entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * @slaves_cnt: number of @slave entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @response_lat: device OCP response latency (in interface clock cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @_int_flags: internal-use hwmod flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @_state: internal-use hwmod state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * @flags: hwmod flags (documented below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * @_lock: spinlock serializing operations on this hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * @node: list node for hwmod list (internal use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @main_clk refers to this module's "main clock," which for our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * purposes is defined as "the functional clock needed for register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * accesses to complete." Modules may not have a main clock if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * interface clock also serves as a main clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * Parameter names beginning with an underscore are managed internally by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * the omap_hwmod code and should not be set during initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * @masters and @slaves are now deprecated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * @parent_hwmod is temporary; there should be no need for it, as this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * information should already be expressed in the OCP interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * structures. @parent_hwmod is present as a workaround until we improve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * multiple register targets across different interconnects).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct omap_hwmod {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct omap_hwmod_class *class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct omap_device *od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct omap_hwmod_rst_info *rst_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct omap_hwmod_omap2_prcm omap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct omap_hwmod_omap4_prcm omap4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } prcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) const char *main_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct clk *_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct omap_hwmod_opt_clk *opt_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) const char *clkdm_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct clockdomain *clkdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct list_head slave_ports; /* connect to *_TA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) void *dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 _sysc_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) void __iomem *_mpu_rt_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spinlock_t _lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct lock_class_key hwmod_key; /* unique lock class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct omap_hwmod_ocp_if *_mpu_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 mpu_rt_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u8 response_lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 rst_lines_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 opt_clks_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u8 slaves_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 hwmods_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 _int_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 _state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 _postsetup_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct omap_hwmod *parent_hwmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct omap_hwmod *omap_hwmod_lookup(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int __init omap_hwmod_setup_one(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct resource *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct ti_sysc_module_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct ti_sysc_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int omap_hwmod_init_module(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) const struct ti_sysc_module_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ti_sysc_cookie *cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int omap_hwmod_enable(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int omap_hwmod_idle(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int omap_hwmod_shutdown(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int omap_hwmod_softreset(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const char *name, struct resource *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int omap_hwmod_for_each_by_class(const char *classname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int (*fn)(struct omap_hwmod *oh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) void *user),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void *user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) extern void __init omap_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Chip variant-specific hwmod init routines - XXX should be converted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * to use initcalls once the initial boot ordering is straightened out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) extern int omap2420_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) extern int omap2430_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) extern int omap3xxx_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) extern int omap44xx_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) extern int omap54xx_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) extern int am33xx_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) extern int dm814x_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) extern int dm816x_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) extern int dra7xx_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int am43xx_hwmod_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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