Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Address mappings and base address for OMAP5 interconnects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * and peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Sricharan <r.sricharan@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASM_SOC_OMAP54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ASM_SOC_OMAP54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Please place only base defines here and put the rest in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * specific headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L4_54XX_BASE			0x4a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define L4_WK_54XX_BASE			0x4ae00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define L4_PER_54XX_BASE		0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define L3_54XX_BASE			0x44000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP54XX_32KSYNCT_BASE		0x4ae04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP54XX_CM_CORE_AON_BASE	0x4a004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP54XX_CM_CORE_BASE		0x4a008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP54XX_PRM_BASE		0x4ae06000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP54XX_PRCM_MPU_BASE		0x48243000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP54XX_SCM_BASE		0x4a002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP54XX_CTRL_BASE		0x4a002800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP54XX_SAR_RAM_BASE		0x4ae26000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* DRA7 specific base addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define L3_MAIN_SN_DRA7XX_BASE		0x44000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define L4_PER1_DRA7XX_BASE		0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define L4_CFG_MPU_DRA7XX_BASE		0x48210000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define L4_PER2_DRA7XX_BASE		0x48400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define L4_PER3_DRA7XX_BASE		0x48800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define L4_CFG_DRA7XX_BASE		0x4A000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define L4_WKUP_DRA7XX_BASE		0x4ae00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRA7XX_CM_CORE_AON_BASE		0x4a005000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRA7XX_CTRL_BASE		0x4a003400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRA7XX_TAP_BASE			0x4ae0c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif /* __ASM_SOC_OMAP555554XX_H */