Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Address mappings and base address for OMAP4 interconnects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * and peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASM_ARCH_OMAP44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ASM_ARCH_OMAP44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Please place only base defines here and put the rest in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * specific headers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L4_44XX_BASE			0x4a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define L4_WK_44XX_BASE			0x4a300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define L4_PER_44XX_BASE		0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define L4_EMU_44XX_BASE		0x54000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define L3_44XX_BASE			0x44000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP44XX_EMIF1_BASE		0x4c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP44XX_EMIF2_BASE		0x4d000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP44XX_DMM_BASE		0x4e000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP4430_32KSYNCT_BASE		0x4a304000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP4430_CM1_BASE		0x4a004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP4430_CM_BASE		OMAP4430_CM1_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP4430_CM2_BASE		0x4a008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP4430_PRM_BASE		0x4a306000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP4430_PRCM_MPU_BASE		0x48243000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP44XX_GPMC_BASE		0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP443X_SCM_BASE		0x4a002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP443X_CTRL_BASE		0x4a100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP44XX_IC_BASE		0x48200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP44XX_IVA_INTC_BASE		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_SIR_IRQ			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP44XX_GIC_DIST_BASE		0x48241000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP44XX_GIC_CPU_BASE		0x48240100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP44XX_IRQ_GIC_START		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP44XX_LOCAL_TWD_BASE		0x48240600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP44XX_L2CACHE_BASE		0x48242000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP44XX_WKUPGEN_BASE		0x48281000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP44XX_MCPDM_BASE		0x40132000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP44XX_SAR_RAM_BASE		0x4a326000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP44XX_MAILBOX_BASE		(L4_44XX_BASE + 0xF4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP44XX_HSUSB_OTG_BASE		(L4_44XX_BASE + 0xAB000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP4_MMU1_BASE			0x55082000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP4_MMU2_BASE			0x4A066000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP44XX_USBTLL_BASE		(L4_44XX_BASE + 0x62000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP44XX_UHH_CONFIG_BASE	(L4_44XX_BASE + 0x64000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP44XX_HSUSB_OHCI_BASE	(L4_44XX_BASE + 0x64800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP44XX_HSUSB_EHCI_BASE	(L4_44XX_BASE + 0x64C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif /* __ASM_ARCH_OMAP44XX_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)