Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SAR_BANK1_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SAR_BANK2_OFFSET		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SAR_BANK3_OFFSET		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SAR_BANK4_OFFSET		0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Scratch pad memory offsets from SAR_BANK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCU_OFFSET0				0xfe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCU_OFFSET1				0xfe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP_TYPE_OFFSET			0xfec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define L2X0_SAVE_OFFSET0			0xff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define L2X0_SAVE_OFFSET1			0xff4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define L2X0_AUXCTRL_OFFSET			0xff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define L2X0_PREFETCH_CTRL_OFFSET		0xffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET		0xa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET		0xa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET	0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET	0xe04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SAR_BACKUP_STATUS_OFFSET		(SAR_BANK3_OFFSET + 0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SAR_SECURE_RAM_SIZE_OFFSET		(SAR_BANK3_OFFSET + 0x504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SAR_SECRAM_SAVED_AT_OFFSET		(SAR_BANK3_OFFSET + 0x508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WAKEUPGENENB_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WAKEUPGENENB_SECURE_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WAKEUPGENENB_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WAKEUPGENENB_SECURE_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0x6b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AUXCOREBOOT0_OFFSET			(SAR_BANK3_OFFSET + 0x6c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AUXCOREBOOT1_OFFSET			(SAR_BANK3_OFFSET + 0x6c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PTMSYNCREQ_MASK_OFFSET			(SAR_BANK3_OFFSET + 0x6cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PTMSYNCREQ_EN_OFFSET			(SAR_BANK3_OFFSET + 0x6d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SAR_BACKUP_STATUS_WAKEUPGEN		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP5_WAKEUPGENENB_OFFSET_CPU0		(SAR_BANK3_OFFSET + 0x9dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0	(SAR_BANK3_OFFSET + 0x9f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP5_WAKEUPGENENB_OFFSET_CPU1		(SAR_BANK3_OFFSET + 0xa04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1	(SAR_BANK3_OFFSET + 0xa18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP5_AUXCOREBOOT0_OFFSET		(SAR_BANK3_OFFSET + 0xa2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP5_AUXCOREBOOT1_OFFSET		(SAR_BANK3_OFFSET + 0x930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP5_AMBA_IF_MODE_OFFSET		(SAR_BANK3_OFFSET + 0xa34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP5_SAR_BACKUP_STATUS_OFFSET		(SAR_BANK3_OFFSET + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif