Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This file contains the processor specific definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * of the TI OMAP24XX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2007 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2007 Nokia Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASM_ARCH_OMAP2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ASM_ARCH_OMAP2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Please place only base defines here and put the rest in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * specific headers. Note also that some of these defines are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * for omap1 to compile without adding ifdefs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define L4_24XX_BASE		0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define L4_WK_243X_BASE		0x49000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define L3_24XX_BASE		0x68000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP24XX_IC_BASE	(L4_24XX_BASE + 0xfe000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP24XX_IVA_INTC_BASE	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP242X_CTRL_BASE	L4_24XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP2420_32KSYNCT_BASE	(L4_24XX_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP2420_PRCM_BASE	(L4_24XX_BASE + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP2420_CM_BASE	(L4_24XX_BASE + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP2420_PRM_BASE	OMAP2420_CM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP2420_SDRC_BASE	(L3_24XX_BASE + 0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP2420_SMS_BASE	0x68008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP2420_GPMC_BASE	0x6800a000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP2430_32KSYNCT_BASE	(L4_WK_243X_BASE + 0x20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP2430_PRCM_BASE	(L4_WK_243X_BASE + 0x6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP2430_CM_BASE	(L4_WK_243X_BASE + 0x6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP2430_PRM_BASE	OMAP2430_CM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP243X_SMS_BASE	0x6C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP243X_SDRC_BASE	0x6D000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP243X_GPMC_BASE	0x6E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP243X_SCM_BASE	(L4_WK_243X_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP243X_CTRL_BASE	OMAP243X_SCM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP243X_HS_BASE	(L4_24XX_BASE + 0x000ac000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* DSP SS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP2420_DSP_BASE	0x58000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP2420_DSP_MEM_BASE	(OMAP2420_DSP_BASE + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP2420_DSP_IPI_BASE	(OMAP2420_DSP_BASE + 0x1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP2420_DSP_MMU_BASE	(OMAP2420_DSP_BASE + 0x2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP243X_DSP_BASE	0x5C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP243X_DSP_MEM_BASE	(OMAP243X_DSP_BASE + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP243X_DSP_MMU_BASE	(OMAP243X_DSP_BASE + 0x1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP24XX_MAILBOX_BASE	(L4_24XX_BASE + 0x94000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Camera */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP24XX_CAMERA_BASE	(L4_24XX_BASE + 0x52000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Security */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP24XX_SEC_BASE	(L4_24XX_BASE + 0xA0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP24XX_SEC_RNG_BASE	(OMAP24XX_SEC_BASE + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP24XX_SEC_DES_BASE	(OMAP24XX_SEC_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP24XX_SEC_AES_BASE	(OMAP24XX_SEC_BASE + 0x6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP24XX_SEC_PKA_BASE	(OMAP24XX_SEC_BASE + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* __ASM_ARCH_OMAP2_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)