^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * omap-secure.h: OMAP Secure infrastructure header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef OMAP_ARCH_OMAP_SECURE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define OMAP_ARCH_OMAP_SECURE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Monitor error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* HAL API error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define API_HAL_RET_VALUE_OK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define API_HAL_RET_VALUE_FAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Secure HAL API flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FLAG_START_CRITICAL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FLAG_IRQFIQ_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FLAG_IRQ_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FLAG_FIQ_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NO_FLAG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Maximum Secure memory storage size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Secure low power HAL API index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP4_HAL_SAVEHW_INDEX 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP4_HAL_SAVEALL_INDEX 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP4_HAL_SAVEGIC_INDEX 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Secure Monitor mode APIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP4_MON_SCU_PWR_INDEX 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP4_MON_L2X0_CTRL_INDEX 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP5_MON_AMBA_IF_INDEX 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Secure PPA(Primary Protected Application) APIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP4_PPA_SERVICE_0 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4_PPA_L2_POR_INDEX 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AM43xx_PPA_SVC_PM_SUSPEND 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AM43xx_PPA_SVC_PM_RESUME 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Secure RX-51 PPA (Primary Protected Application) APIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RX51_PPA_HWRNG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RX51_PPA_L2_INVAL 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RX51_PPA_WRITE_ACR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 arg1, u32 arg2, u32 arg3, u32 arg4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void omap_smccc_smc(u32 fn, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern void omap_smc1(u32 fn, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern phys_addr_t omap_secure_ram_mempool_base(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern int omap_secure_ram_reserve_memblock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern u32 save_secure_ram_context(u32 args_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 arg1, u32 arg2, u32 arg3, u32 arg4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern bool optee_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void omap_secure_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void set_cntfreq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void set_cntfreq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* __ASSEMBLER__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* OMAP_ARCH_OMAP_SECURE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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