Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP Secure API infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "omap-secure.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static phys_addr_t omap_secure_memblock_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) bool optee_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	ARM_SMCCC_OWNER_SIP, (func_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void __init omap_optee_init_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	 * We only check that the OP-TEE node is present and available. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	 * OP-TEE kernel driver is not needed for the type of interaction made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	 * with OP-TEE here so the driver's status is not checked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	np = of_find_node_by_path("/firmware/optee");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (np && of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		optee_available = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * omap_sec_dispatcher: Routine to dispatch low power secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * service routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @idx: The HAL API index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @flag: The flag indicating criticality of operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @nargs: Number of valid arguments out of four.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @arg1, arg2, arg3 args4: Parameters passed to secure API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * Return the non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 							 u32 arg3, u32 arg4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 param[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	param[0] = nargs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	param[1] = arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	param[2] = arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	param[3] = arg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	param[4] = arg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * Secure API needs physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * pointer for the parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	outer_clean_range(__pa(param), __pa(param + 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ret = omap_smc2(idx, flag, __pa(param));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) void omap_smccc_smc(u32 fn, u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		      0, 0, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) void omap_smc1(u32 fn, u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * If this platform has OP-TEE installed we use ARM SMC calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * otherwise fall back to the OMAP ROM style calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (optee_available)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		omap_smccc_smc(fn, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		_omap_smc1(fn, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Allocate the memory to save secure ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int __init omap_secure_ram_reserve_memblock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u32 size = OMAP_SECURE_RAM_STORAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	size = ALIGN(size, SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) phys_addr_t omap_secure_ram_mempool_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return omap_secure_memblock_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 omap3_save_secure_ram(void __iomem *addr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32 param[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (size != OMAP3_SAVE_SECURE_RAM_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return OMAP3_SAVE_SECURE_RAM_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	param[0] = 4;		/* Number of arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	param[1] = __pa(addr);	/* Physical address for saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	param[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	param[3] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	param[4] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ret = save_secure_ram_context(__pa(param));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * @idx: The PPA API index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * @process: Process ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * @flag: The flag indicating criticality of operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * @nargs: Number of valid arguments out of four.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @arg1, arg2, arg3 args4: Parameters passed to secure API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * Return the non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *       it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			   u32 arg1, u32 arg2, u32 arg3, u32 arg4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32 param[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	param[1] = arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	param[2] = arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	param[3] = arg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	param[4] = arg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * Secure API needs physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * pointer for the parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	local_fiq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	outer_clean_range(__pa(param), __pa(param + 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret = omap_smc3(idx, process, flag, __pa(param));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	local_fiq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  *  @set_bits: bits to set in ACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  *  @clr_bits: bits to clear in ACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * Return the non-zero error value on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 acr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Read ACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	acr &= ~clear_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	acr |= set_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				      0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				      FLAG_START_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				      1, acr, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * rx51_secure_rng_call: Routine for HW random generator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	return rx51_secure_dispatcher(RX51_PPA_HWRNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				      0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				      NO_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				      3, ptr, count, flag, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void __init omap_secure_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	omap_optee_init_check();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * address after MMU has been re-enabled after CPU1 has been woken up again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * Otherwise the ROM code will attempt to use the earlier physical return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * address that got set with MMU off when waking up CPU1. Only used on secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				       FLAG_START_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				       0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct notifier_block secure_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.notifier_call = cpu_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int __init secure_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	cpu_pm_register_notifier(&secure_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) omap_arch_initcall(secure_pm_init);