^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Secondary CPU startup routine source file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2014 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Interface functions needed for the SMP. This file is based on arm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * realview smp platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2003 ARM Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "omap44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Physical address needed since MMU not enabled yet on secondary core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AUX_CORE_BOOT0_PA 0x48281800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define API_HYP_ENTRY 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ENTRY(omap_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) b secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Should never get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) again: wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) b again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ENDPROC(omap_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * OMAP5 specific entry point for secondary CPU to jump from ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * code. This routine also provides a holding flag into which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * secondary core is held until we're ready for it to initialise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The primary core will update this flag using a hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * register AuxCoreBoot0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ENTRY(omap5_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ldr r0, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mov r0, r0, lsr #5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mrc p15, 0, r4, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) and r4, r4, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cmp r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) bne wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) b omap_secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ENDPROC(omap5_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Same as omap5_secondary_startup except we call into the ROM to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * enable HYP mode first. This is called instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * omap5_secondary_startup if the primary CPU was put into HYP mode by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * the boot loader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .arch armv7-a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .arch_extension sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ENTRY(omap5_secondary_hyp_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ldr r0, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mov r0, r0, lsr #5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mrc p15, 0, r4, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) and r4, r4, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) cmp r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bne wait_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ldr r12, =API_HYP_ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) badr r0, hyp_boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hyp_boot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) b omap_secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ENDPROC(omap5_secondary_hyp_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * OMAP4 specific entry point for secondary CPU to jump from ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * code. This routine also provides a holding flag into which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * secondary core is held until we're ready for it to initialise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * The primary core will update this flag using a hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * register AuxCoreBoot0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ENTRY(omap4_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) hold: ldr r12,=0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) smc #0 @ read from AuxCoreBoot0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mov r0, r0, lsr #9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mrc p15, 0, r4, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) and r4, r4, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cmp r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bne hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * we've been released from the wait loop,secondary_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * should now contain the SVC stack for this core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) b omap_secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ENDPROC(omap4_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ENTRY(omap4460_secondary_startup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) hold_2: ldr r12,=0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) smc #0 @ read from AuxCoreBoot0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mov r0, r0, lsr #9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mrc p15, 0, r4, c0, c0, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) and r4, r4, #0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) cmp r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bne hold_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * GIC distributor control register has changed between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * CortexA9 r1pX and r2pX. The Control Register secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * banked version is now composed of 2 bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * bit 0 == Secure Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * bit 1 == Non-Secure Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * The Non-Secure banked register has not changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Because the ROM Code is based on the r1pX GIC, the CPU1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * GIC restoration will cause a problem to CPU0 Non-Secure SW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * The workaround must be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * 1) Before doing the CPU1 wakeup, CPU0 must disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * the GIC distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * 2) CPU1 must re-enable the GIC distributor on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * it's wakeup path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ldr r1, =OMAP44XX_GIC_DIST_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ldr r0, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) orr r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) str r0, [r1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * we've been released from the wait loop,secondary_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * should now contain the SVC stack for this core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) b omap_secondary_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ENDPROC(omap4460_secondary_startup)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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