Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * MSDI IP block reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * XXX What about pad muxing?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "omap_hwmod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "omap_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *     from the IP block's base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MSDI_CON_OFFSET				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Register bitfields in the CON register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MSDI_CON_POW_MASK			BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MSDI_CON_CLKD_MASK			(0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSDI_CON_CLKD_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MSDI_TARGET_RESET_CLKD		0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * omap_msdi_reset - reset the MSDI IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * @oh: struct omap_hwmod *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * fields set inside its CON register for a reset to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * successfully.  This is not documented in the TRM.  For CLKD, we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * the value that results in the lowest possible clock rate, to attempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * to avoid disturbing any cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int omap_msdi_reset(struct omap_hwmod *oh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u16 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	int c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	/* Write to the SOFTRESET bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	omap_hwmod_softreset(oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* Enable the MSDI core and internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	v |= MSDI_CON_POW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	/* Poll on RESETDONE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			   & SYSS_RESETDONE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			  MAX_MODULE_SOFTRESET_WAIT, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	if (c == MAX_MODULE_SOFTRESET_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		pr_warn("%s: %s: softreset failed (waited %d usec)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		pr_debug("%s: %s: softreset in %d usec\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			 oh->name, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	/* Disable the MSDI internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	v &= ~MSDI_CON_CLKD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }