Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * IO mappings for OMAP2+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * IO definitions for TI OMAP processors and boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copied from arch/arm/mach-sa1100/include/mach/io.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 1997-1999 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2009-2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OMAP2_L3_IO_OFFSET	0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OMAP2_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OMAP2_L4_IO_OFFSET	0xb2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP2_L4_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OMAP4_L3_IO_OFFSET	0xb4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OMAP4_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AM33XX_L4_WK_IO_OFFSET	0xb5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AM33XX_L4_WK_IO_ADDRESS(pa)	IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OMAP4_L3_PER_IO_OFFSET	0xb1100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OMAP4_L3_PER_IO_ADDRESS(pa)	IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP2_EMU_IO_OFFSET		0xaa800000	/* Emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OMAP2_EMU_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * Omap2 specific IO mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* We map both L3 and L4 on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define L3_24XX_PHYS	L3_24XX_BASE	/* 0x68000000 --> 0xf8000000*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define L3_24XX_VIRT	(L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define L3_24XX_SIZE	SZ_1M		/* 44kB of 128MB used, want 1MB sect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define L4_24XX_PHYS	L4_24XX_BASE	/* 0x48000000 --> 0xfa000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define L4_24XX_VIRT	(L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define L4_24XX_SIZE	SZ_1M		/* 1MB of 128MB used, want 1MB sect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define L4_WK_243X_PHYS		L4_WK_243X_BASE	/* 0x49000000 --> 0xfb000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define L4_WK_243X_VIRT		(L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define L4_WK_243X_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OMAP243X_GPMC_PHYS	OMAP243X_GPMC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OMAP243X_GPMC_VIRT	(OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 						/* 0x6e000000 --> 0xfe000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OMAP243X_GPMC_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define OMAP243X_SDRC_PHYS	OMAP243X_SDRC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 						/* 0x6D000000 --> 0xfd000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OMAP243X_SDRC_VIRT	(OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define OMAP243X_SDRC_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OMAP243X_SMS_PHYS	OMAP243X_SMS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 						/* 0x6c000000 --> 0xfc000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define OMAP243X_SMS_VIRT	(OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OMAP243X_SMS_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* 2420 IVA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DSP_MEM_2420_PHYS	OMAP2420_DSP_MEM_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 						/* 0x58000000 --> 0xfc100000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DSP_MEM_2420_VIRT	0xfc100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DSP_MEM_2420_SIZE	0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DSP_IPI_2420_PHYS	OMAP2420_DSP_IPI_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 						/* 0x59000000 --> 0xfc128000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DSP_IPI_2420_VIRT	0xfc128000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DSP_IPI_2420_SIZE	SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DSP_MMU_2420_PHYS	OMAP2420_DSP_MMU_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 						/* 0x5a000000 --> 0xfc129000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DSP_MMU_2420_VIRT	0xfc129000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DSP_MMU_2420_SIZE	SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* 2430 IVA2.1 - currently unmapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * Omap3 specific IO mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* We map both L3 and L4 on OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define L3_34XX_PHYS		L3_34XX_BASE	/* 0x68000000 --> 0xf8000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define L3_34XX_VIRT		(L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define L3_34XX_SIZE		SZ_1M   /* 44kB of 128MB used, want 1MB sect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define L4_34XX_PHYS		L4_34XX_BASE	/* 0x48000000 --> 0xfa000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define L4_34XX_VIRT		(L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * AM33XX specific IO mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define L4_WK_AM33XX_PHYS	L4_WK_AM33XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define L4_WK_AM33XX_VIRT	(L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define L4_WK_AM33XX_SIZE	SZ_4M   /* 1MB of 128MB used, want 1MB sect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * Need to look at the Size 4M for L4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * VPOM3430 was not working for Int controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define L4_PER_34XX_PHYS	L4_PER_34XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 						/* 0x49000000 --> 0xfb000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define L4_PER_34XX_VIRT	(L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define L4_PER_34XX_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define L4_EMU_34XX_PHYS	L4_EMU_34XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 						/* 0x54000000 --> 0xfe800000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define L4_EMU_34XX_VIRT	(L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define L4_EMU_34XX_SIZE	SZ_8M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP34XX_GPMC_PHYS	OMAP34XX_GPMC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 						/* 0x6e000000 --> 0xfe000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP34XX_GPMC_VIRT	(OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP34XX_GPMC_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP343X_SMS_PHYS	OMAP343X_SMS_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 						/* 0x6c000000 --> 0xfc000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP343X_SMS_VIRT	(OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP343X_SMS_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP343X_SDRC_PHYS	OMAP343X_SDRC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 						/* 0x6D000000 --> 0xfd000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP343X_SDRC_VIRT	(OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP343X_SDRC_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* 3430 IVA - currently unmapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * Omap4 specific IO mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* We map both L3 and L4 on OMAP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define L3_44XX_PHYS		L3_44XX_BASE	/* 0x44000000 --> 0xf8000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define L3_44XX_VIRT		(L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define L3_44XX_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define L4_44XX_PHYS		L4_44XX_BASE	/* 0x4a000000 --> 0xfc000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define L4_44XX_VIRT		(L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define L4_44XX_SIZE		SZ_4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define L4_PER_44XX_PHYS	L4_PER_44XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 						/* 0x48000000 --> 0xfa000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define L4_PER_44XX_VIRT	(L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define L4_PER_44XX_SIZE	SZ_4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define L4_ABE_44XX_PHYS	L4_ABE_44XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 						/* 0x49000000 --> 0xfb000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define L4_ABE_44XX_VIRT	(L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define L4_ABE_44XX_SIZE	SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * Omap5 specific IO mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define L3_54XX_PHYS		L3_54XX_BASE	/* 0x44000000 --> 0xf8000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define L3_54XX_VIRT		(L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define L3_54XX_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define L4_54XX_PHYS		L4_54XX_BASE	/* 0x4a000000 --> 0xfc000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define L4_54XX_VIRT		(L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define L4_54XX_SIZE		SZ_4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define L4_WK_54XX_PHYS		L4_WK_54XX_BASE	/* 0x4ae00000 --> 0xfce00000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define L4_WK_54XX_VIRT		(L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define L4_WK_54XX_SIZE		SZ_2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define L4_PER_54XX_PHYS	L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define L4_PER_54XX_VIRT	(L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define L4_PER_54XX_SIZE	SZ_4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * DRA7xx specific IO mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * everything is just inefficient, since, there are too many address holes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define L3_MAIN_SN_DRA7XX_PHYS		L3_MAIN_SN_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define L3_MAIN_SN_DRA7XX_VIRT		(L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define L3_MAIN_SN_DRA7XX_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * L4_PER1_DRA7XX_PHYS	(0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *	(0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define L4_PER1_DRA7XX_PHYS		L4_PER1_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define L4_PER1_DRA7XX_VIRT		(L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define L4_PER1_DRA7XX_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * L4_CFG_MPU_DRA7XX_PHYS	(0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  *	(0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * NOTE: This is a bit of an orphan memory map sitting isolated in TRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define L4_CFG_MPU_DRA7XX_PHYS		L4_CFG_MPU_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define L4_CFG_MPU_DRA7XX_VIRT		(L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define L4_CFG_MPU_DRA7XX_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * L4_PER2_DRA7XX_PHYS	(0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  *	(0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define L4_PER2_DRA7XX_PHYS		L4_PER2_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define L4_PER2_DRA7XX_VIRT		(L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define L4_PER2_DRA7XX_SIZE		SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * L4_PER3_DRA7XX_PHYS	(0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  *	(0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define L4_PER3_DRA7XX_PHYS		L4_PER3_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define L4_PER3_DRA7XX_VIRT		(L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define L4_PER3_DRA7XX_SIZE		SZ_2M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * L4_CFG_DRA7XX_PHYS	(0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *	(0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define L4_CFG_DRA7XX_PHYS		L4_CFG_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define L4_CFG_DRA7XX_VIRT		(L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define L4_CFG_DRA7XX_SIZE		(SZ_1M + SZ_2M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * L4_WKUP_DRA7XX_PHYS	(0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *	(0x4AE00000<->4AF00000)	<=> (0xFCE00000<->0xFCF00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define L4_WKUP_DRA7XX_PHYS		L4_WKUP_DRA7XX_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define L4_WKUP_DRA7XX_VIRT		(L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define L4_WKUP_DRA7XX_SIZE		SZ_1M