^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap2/io.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * OMAP2 I/O mapping code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007-2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Juha Yrjola <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Syed Khasim <x0khasim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "omap_hwmod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "voltage.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "clock2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "clock3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "serial.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "cm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "cm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "cm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "cm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "prcm_mpu44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "prminst44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "prm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "prm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "prm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "prm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "opp2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "omap-secure.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * omap_clk_soc_init: points to a function that does the SoC-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * clock initializations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int (*omap_clk_soc_init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * The machine specific code may provide the extra mapping besides the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * default mapping provided here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct map_desc omap24xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .virtual = L3_24XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .pfn = __phys_to_pfn(L3_24XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .length = L3_24XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .virtual = L4_24XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .pfn = __phys_to_pfn(L4_24XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .length = L4_24XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_SOC_OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct map_desc omap242x_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .virtual = DSP_MEM_2420_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .length = DSP_MEM_2420_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .virtual = DSP_IPI_2420_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .length = DSP_IPI_2420_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .virtual = DSP_MMU_2420_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .length = DSP_MMU_2420_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_SOC_OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct map_desc omap243x_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .virtual = L4_WK_243X_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .length = L4_WK_243X_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .virtual = OMAP243X_GPMC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .length = OMAP243X_GPMC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .virtual = OMAP243X_SDRC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .length = OMAP243X_SDRC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .virtual = OMAP243X_SMS_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .length = OMAP243X_SMS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct map_desc omap34xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .virtual = L3_34XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .pfn = __phys_to_pfn(L3_34XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .length = L3_34XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .virtual = L4_34XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .pfn = __phys_to_pfn(L4_34XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .length = L4_34XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .virtual = OMAP34XX_GPMC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .length = OMAP34XX_GPMC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .virtual = OMAP343X_SMS_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .length = OMAP343X_SMS_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .virtual = OMAP343X_SDRC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .length = OMAP343X_SDRC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .virtual = L4_PER_34XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .length = L4_PER_34XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .virtual = L4_EMU_34XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .length = L4_EMU_34XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct map_desc omapti81xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .virtual = L4_34XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .pfn = __phys_to_pfn(L4_34XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .length = L4_34XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct map_desc omapam33xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .virtual = L4_34XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .pfn = __phys_to_pfn(L4_34XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .length = L4_34XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .virtual = L4_WK_AM33XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .length = L4_WK_AM33XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct map_desc omap44xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .virtual = L3_44XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pfn = __phys_to_pfn(L3_44XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .length = L3_44XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .virtual = L4_44XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .pfn = __phys_to_pfn(L4_44XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .length = L4_44XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .virtual = L4_PER_44XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .length = L4_PER_44XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #ifdef CONFIG_SOC_OMAP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct map_desc omap54xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .virtual = L3_54XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .pfn = __phys_to_pfn(L3_54XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .length = L3_54XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .virtual = L4_54XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .pfn = __phys_to_pfn(L4_54XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .length = L4_54XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .virtual = L4_WK_54XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .length = L4_WK_54XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .virtual = L4_PER_54XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .length = L4_PER_54XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct map_desc dra7xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .virtual = L4_CFG_MPU_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .length = L4_CFG_MPU_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .virtual = L3_MAIN_SN_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .length = L3_MAIN_SN_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .virtual = L4_PER1_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .length = L4_PER1_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .virtual = L4_PER2_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .length = L4_PER2_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .virtual = L4_PER3_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .length = L4_PER3_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .virtual = L4_CFG_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .length = L4_CFG_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .virtual = L4_WKUP_DRA7XX_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .length = L4_WKUP_DRA7XX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_SOC_OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void __init omap242x_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef CONFIG_SOC_OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void __init omap243x_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void __init omap3_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void __init ti81xx_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void __init am33xx_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __init omap4_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) omap_barriers_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #ifdef CONFIG_SOC_OMAP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void __init omap5_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) omap_barriers_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void __init dra7xx_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) omap_barriers_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Sets the CORE DPLL3 M2 divider to the same value that it's at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * currently. This has the effect of setting the SDRC SDRAM AC timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * registers to the values currently defined by the kernel. Currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * only defined for OMAP3; will return 0 if called on OMAP2. Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * or passes along the return value of clk_set_rate().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int __init _omap2_init_reprogram_sdrc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct clk *dpll3_m2_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int v = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (IS_ERR(dpll3_m2_ck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) rate = clk_get_rate(dpll3_m2_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) v = clk_set_rate(dpll3_m2_ck, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pr_err("dpll3_m2_clk rate change failed: %d\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk_put(dpll3_m2_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void __init __maybe_unused omap_hwmod_init_postsetup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 postsetup_state = _HWMOD_STATE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Set the default postsetup state for all hwmods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #ifdef CONFIG_SOC_OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) void __init omap2420_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) omap2xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) omap2xxx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) omap242x_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) omap242x_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) omap2420_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) omap_clk_soc_init = omap2420_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rate_table = omap2420_rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) void __init omap2420_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) omap_pm_soc_init = omap2_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #ifdef CONFIG_SOC_OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) void __init omap2430_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) omap2xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) omap2xxx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) omap243x_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) omap243x_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) omap2430_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) omap_clk_soc_init = omap2430_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) rate_table = omap2430_rate_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) void __init omap2430_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) omap_pm_soc_init = omap2_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Currently only board-omap3beagle.c should call this because of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) void __init omap3_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) omap3xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) omap3xxx_check_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) omap3xxx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) omap3xxx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) omap3xxx_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) omap3xxx_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void __init omap3430_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) omap3_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) omap_clk_soc_init = omap3430_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void __init omap35xx_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) omap3_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) omap_clk_soc_init = omap3430_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) void __init omap3630_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) omap3_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) omap_clk_soc_init = omap3630_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void __init am35xx_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) omap3_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) omap_clk_soc_init = am35xx_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) void __init omap3_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) omap_pm_soc_init = omap3_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) void __init ti81xx_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) omap_pm_soc_init = omap_pm_nop_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void __init ti814x_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) omap2_set_globals_tap(TI814X_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) omap3xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ti81xx_check_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) omap3xxx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) omap3xxx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ti814x_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dm814x_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) omap_clk_soc_init = dm814x_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void __init ti816x_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) omap2_set_globals_tap(TI816X_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) omap3xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ti81xx_check_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) omap3xxx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) omap3xxx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ti816x_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dm816x_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) omap_clk_soc_init = dm816x_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #ifdef CONFIG_SOC_AM33XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) void __init am33xx_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) omap2_set_globals_tap(AM335X_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) omap3xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) am33xx_check_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) am33xx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) am33xx_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) am33xx_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) omap_clk_soc_init = am33xx_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) void __init am33xx_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) omap_pm_soc_init = amx3_common_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #ifdef CONFIG_SOC_AM43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) void __init am43xx_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) omap2_set_globals_tap(AM335X_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) omap3xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) am33xx_check_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) am43xx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) am43xx_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) am43xx_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) omap_l2_cache_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) omap_clk_soc_init = am43xx_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void __init am43xx_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) omap_pm_soc_init = amx3_common_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) void __init omap4430_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) omap2_set_globals_tap(OMAP443X_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) omap4xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) omap4xxx_check_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) omap4_sar_ram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) omap4_mpuss_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) omap4_pm_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) omap44xx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) omap44xx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) omap44xx_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) omap44xx_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) omap_l2_cache_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) omap_clk_soc_init = omap4xxx_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) void __init omap4430_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) omap_pm_soc_init = omap4_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #ifdef CONFIG_SOC_OMAP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) void __init omap5_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) omap2_set_globals_tap(OMAP54XX_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) omap5xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) omap4_sar_ram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) omap4_mpuss_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) omap4_pm_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) omap54xx_voltagedomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) omap54xx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) omap54xx_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) omap54xx_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) omap_clk_soc_init = omap5xxx_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) void __init omap5_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) omap_pm_soc_init = omap4_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) void __init dra7xx_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) omap2_set_globals_tap(DRA7XX_CLASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) omap2_control_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) omap4_pm_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) omap2_prcm_base_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dra7xxx_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dra7xx_powerdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dra7xx_clockdomains_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dra7xx_hwmod_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) omap_hwmod_init_postsetup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) omap_clk_soc_init = dra7xx_dt_clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) omap_secure_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) void __init dra7xx_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) omap_pm_soc_init = omap4_pm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct omap_sdrc_params *sdrc_cs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) omap_sram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (cpu_is_omap24xx() || omap3_has_sdrc()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) _omap2_init_reprogram_sdrc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int __init omap_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!omap_clk_soc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ti_clk_init_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) omap2_clk_setup_ll_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = omap_control_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = omap_prcm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ti_dt_clk_init_retry_clks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ti_dt_clockdomains_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = omap_clk_soc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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