^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap2/id.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * OMAP2 CPU identification code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Written by Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2009-11 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_SOC_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4_SILICON_TYPE_STANDARD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP_SOC_MAX_NAME_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static unsigned int omap_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 omap_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int omap_rev(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return omap_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXPORT_SYMBOL(omap_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int omap_type(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static u32 val = OMAP2_DEVICETYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (val < OMAP2_DEVICETYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (soc_is_omap24xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) } else if (soc_is_ti81xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else if (soc_is_am33xx() || soc_is_am43xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else if (soc_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } else if (soc_is_omap44xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) val &= OMAP5_DEVICETYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val >>= 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_err("Cannot detect omap type!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val &= OMAP2_DEVICETYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) EXPORT_SYMBOL(omap_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*----------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP_TAP_IDCODE 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP_TAP_DIE_ID_0 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP_TAP_DIE_ID_1 0x021C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP_TAP_DIE_ID_2 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP_TAP_DIE_ID_3 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP_TAP_DIE_ID_44XX_0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP_TAP_DIE_ID_44XX_1 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP_TAP_DIE_ID_44XX_2 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP_TAP_DIE_ID_44XX_3 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct omap_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 hawkeye; /* Silicon type (Hawkeye id) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 dev; /* Device type from production_id reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 type; /* Combined type id copied to omap_revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Register values to detect the OMAP version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct omap_id omap_ids[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void __iomem *tap_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u16 tap_prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void omap_get_die_id(struct omap_die_id *odi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int __init omap_feed_randpool(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct omap_die_id odi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Throw the die ID into the entropy pool at boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) omap_get_die_id(&odi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) add_device_randomness(&odi, sizeof(odi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) omap_device_initcall(omap_feed_randpool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __init omap2xxx_check_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 idcode, prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 hawkeye;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 dev_type, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct omap_die_id odi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) idcode = read_tap_reg(OMAP_TAP_IDCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) prod_id = read_tap_reg(tap_prod_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) hawkeye = (idcode >> 12) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rev = (idcode >> 28) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_type = (prod_id >> 16) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) omap_get_die_id(&odi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) odi.id_1, (odi.id_1 >> 28) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) prod_id, dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Check hawkeye ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (hawkeye == omap_ids[i].hawkeye)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (i == ARRAY_SIZE(omap_ids)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) printk(KERN_ERR "Unknown OMAP CPU id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (dev_type == omap_ids[j].dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (j == ARRAY_SIZE(omap_ids)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) omap_ids[i].type >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) j = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_info("%s", soc_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if ((omap_rev() >> 8) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_cont("%s", soc_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP3_SHOW_FEATURE(feat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (omap3_has_ ##feat()) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void __init omap3_cpuinfo(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const char *cpu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) char buf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) memset(buf, 0, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * OMAP3430 and OMAP3530 are assumed to be same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * on available features. Upon detection, update the CPU id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * and CPU class bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (soc_is_omap3630()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (omap3_has_iva() && omap3_has_sgx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } else if (omap3_has_iva()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cpu_name = "DM3725";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else if (omap3_has_sgx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cpu_name = "OMAP3615/AM3715";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else if (soc_is_am35xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else if (soc_is_ti816x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) cpu_name = "TI816X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else if (soc_is_am335x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cpu_name = "AM335X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else if (soc_is_am437x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cpu_name = "AM437x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else if (soc_is_ti814x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cpu_name = "TI814X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else if (omap3_has_iva() && omap3_has_sgx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cpu_name = "OMAP3430/3530";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } else if (omap3_has_iva()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cpu_name = "OMAP3525";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else if (omap3_has_sgx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cpu_name = "OMAP3515";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cpu_name = "OMAP3503";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Print verbose information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) OMAP3_SHOW_FEATURE(l2cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) OMAP3_SHOW_FEATURE(iva);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) OMAP3_SHOW_FEATURE(sgx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) OMAP3_SHOW_FEATURE(neon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) OMAP3_SHOW_FEATURE(isp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) OMAP3_SHOW_FEATURE(192mhz_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (*(buf + n - 1) == ' ')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) n--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pr_info("%s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP3_CHECK_FEATURE(status,feat) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (((status & OMAP3_ ##feat## _MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) omap_features |= OMAP3_HAS_ ##feat; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void __init omap3xxx_check_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) omap_features = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) OMAP3_CHECK_FEATURE(status, L2CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) OMAP3_CHECK_FEATURE(status, IVA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) OMAP3_CHECK_FEATURE(status, SGX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) OMAP3_CHECK_FEATURE(status, NEON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) OMAP3_CHECK_FEATURE(status, ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (soc_is_omap3630())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) omap_features |= OMAP3_HAS_192MHZ_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (soc_is_omap3430() || soc_is_omap3630())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) omap_features |= OMAP3_HAS_IO_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) omap_rev() == OMAP3430_REV_ES3_1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) omap_features |= OMAP3_HAS_SDRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * am35x fixups:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * reserved and therefore return 0 when read. Unfortunately,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * mean that a feature is present even though it isn't so clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * the incorrectly set feature bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (soc_is_am35xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * TODO: Get additional info (where applicable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * e.g. Size of L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) omap3_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void __init omap4xxx_check_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 si_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) si_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) omap_features = OMAP4_HAS_PERF_SILICON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void __init ti81xx_check_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) omap_features = OMAP3_HAS_NEON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) omap3_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void __init am33xx_check_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) omap_features = OMAP3_HAS_NEON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (status & AM33XX_SGX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) omap_features |= OMAP3_HAS_SGX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) omap3_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void __init omap3xxx_check_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) const char *cpu_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 cpuid, idcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 hawkeye;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * We cannot access revision registers on ES1.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * If the processor type is Cortex-A8 and the revision is 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * it means its Cortex r0p0 which is 3430 ES1.0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) cpuid = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) omap_revision = OMAP3430_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Detection for 34xx ES2.0 and above can be done with just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * hawkeye and rev. See TRM 1.5.2 Device Identification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Note that rev does not map directly to our defined processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * revision numbers as ES1.0 uses value 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) idcode = read_tap_reg(OMAP_TAP_IDCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hawkeye = (idcode >> 12) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rev = (idcode >> 28) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) switch (hawkeye) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case 0xb7ae:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Handle 34xx/35xx devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case 0: /* Take care of early samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) omap_revision = OMAP3430_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cpu_rev = "2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) omap_revision = OMAP3430_REV_ES2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cpu_rev = "2.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) omap_revision = OMAP3430_REV_ES3_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cpu_rev = "3.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) omap_revision = OMAP3430_REV_ES3_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cpu_rev = "3.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Use the latest known revision as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) omap_revision = OMAP3430_REV_ES3_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cpu_rev = "3.1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case 0xb868:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Handle OMAP/AM 3505/3517 devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Set the device to be OMAP3517 here. Actual device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * is identified later based on the features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) omap_revision = AM35XX_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) omap_revision = AM35XX_REV_ES1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cpu_rev = "1.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case 0xb891:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Handle 36xx devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) switch(rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case 0: /* Take care of early samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) omap_revision = OMAP3630_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) omap_revision = OMAP3630_REV_ES1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cpu_rev = "1.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) omap_revision = OMAP3630_REV_ES1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cpu_rev = "1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case 0xb81e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) omap_revision = TI8168_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) omap_revision = TI8168_REV_ES1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cpu_rev = "1.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) omap_revision = TI8168_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cpu_rev = "2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) omap_revision = TI8168_REV_ES2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cpu_rev = "2.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 0xb944:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) omap_revision = AM335X_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) omap_revision = AM335X_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cpu_rev = "2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) omap_revision = AM335X_REV_ES2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cpu_rev = "2.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 0xb98c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) omap_revision = AM437X_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) omap_revision = AM437X_REV_ES1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cpu_rev = "1.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) omap_revision = AM437X_REV_ES1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cpu_rev = "1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 0xb8f2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case 0xb968:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) omap_revision = TI8148_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cpu_rev = "1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) omap_revision = TI8148_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cpu_rev = "2.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) omap_revision = TI8148_REV_ES2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cpu_rev = "2.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Unknown default to latest silicon rev as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) omap_revision = OMAP3630_REV_ES1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cpu_rev = "1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hawkeye);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) sprintf(soc_rev, "ES%s", cpu_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void __init omap4xxx_check_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 idcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u16 hawkeye;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * The IC rev detection is done with hawkeye and rev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * Note that rev does not map directly to defined processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * revision numbers as ES1.0 uses value 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) idcode = read_tap_reg(OMAP_TAP_IDCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hawkeye = (idcode >> 12) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rev = (idcode >> 28) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Use ARM register to detect the correct ES version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) idcode = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rev = (idcode & 0xf) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) switch (hawkeye) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case 0xb852:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) omap_revision = OMAP4430_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) omap_revision = OMAP4430_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 0xb95c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) omap_revision = OMAP4430_REV_ES2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) omap_revision = OMAP4430_REV_ES2_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) omap_revision = OMAP4430_REV_ES2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case 0xb94e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) omap_revision = OMAP4460_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) omap_revision = OMAP4460_REV_ES1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case 0xb975:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) omap_revision = OMAP4470_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Unknown default to latest silicon rev as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) omap_revision = OMAP4430_REV_ES2_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (omap_rev() >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pr_info("%s %s\n", soc_name, soc_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void __init omap5xxx_check_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 idcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u16 hawkeye;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) idcode = read_tap_reg(OMAP_TAP_IDCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) hawkeye = (idcode >> 12) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rev = (idcode >> 28) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) switch (hawkeye) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case 0xb942:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* No support for ES1.0 Test chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) omap_revision = OMAP5430_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case 0xb998:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* No support for ES1.0 Test chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) omap_revision = OMAP5432_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Unknown default to latest silicon rev as default*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) omap_revision = OMAP5430_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pr_info("%s %s\n", soc_name, soc_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) void __init dra7xxx_check_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 idcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u16 hawkeye;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u8 rev, package;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct omap_die_id odi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) omap_get_die_id(&odi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) package = (odi.id_2 >> 16) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) idcode = read_tap_reg(OMAP_TAP_IDCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hawkeye = (idcode >> 12) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rev = (idcode >> 28) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) switch (hawkeye) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case 0xbb50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) switch (package) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) omap_revision = DRA762_ABZ_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) omap_revision = DRA762_ACD_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) omap_revision = DRA762_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case 0xb990:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) omap_revision = DRA752_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) omap_revision = DRA752_REV_ES1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) omap_revision = DRA752_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case 0xb9bc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) switch (rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) omap_revision = DRA722_REV_ES1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) omap_revision = DRA722_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) omap_revision = DRA722_REV_ES2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Unknown default to latest silicon rev as default*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __func__, idcode, hawkeye, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) omap_revision = DRA752_REV_ES2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) (omap_rev() >> 8) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pr_info("%s %s\n", soc_name, soc_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * Set up things for map_io and processor detection later on. Gets called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * pretty much first thing from board init. For multi-omap, this gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * detect the exact revision later on in omap2_detect_revision() once map_io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) omap_revision = class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) tap_base = tap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* XXX What is this intended to do? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (soc_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) tap_prod_id = 0x0210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) tap_prod_id = 0x0208;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #ifdef CONFIG_SOC_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const char * const omap_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [OMAP2_DEVICE_TYPE_TEST] = "TST",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [OMAP2_DEVICE_TYPE_EMU] = "EMU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [OMAP2_DEVICE_TYPE_SEC] = "HS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [OMAP2_DEVICE_TYPE_GP] = "GP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [OMAP2_DEVICE_TYPE_BAD] = "BAD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const char * __init omap_get_family(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (soc_is_omap24xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return kasprintf(GFP_KERNEL, "OMAP2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) else if (soc_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return kasprintf(GFP_KERNEL, "OMAP3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) else if (soc_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return kasprintf(GFP_KERNEL, "OMAP4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) else if (soc_is_omap54xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return kasprintf(GFP_KERNEL, "OMAP5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) else if (soc_is_am33xx() || soc_is_am335x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return kasprintf(GFP_KERNEL, "AM33xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) else if (soc_is_am43xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return kasprintf(GFP_KERNEL, "AM43xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) else if (soc_is_dra7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return kasprintf(GFP_KERNEL, "DRA7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return kasprintf(GFP_KERNEL, "Unknown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) type_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return sprintf(buf, "%s\n", omap_types[omap_type()]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static DEVICE_ATTR_RO(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct attribute *omap_soc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) &dev_attr_type.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ATTRIBUTE_GROUPS(omap_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void __init omap_soc_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct soc_device *soc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct soc_device_attribute *soc_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!soc_dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) soc_dev_attr->machine = soc_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) soc_dev_attr->family = omap_get_family();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) soc_dev_attr->revision = soc_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) soc_dev_attr->custom_attr_group = omap_soc_groups[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) soc_dev = soc_device_register(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (IS_ERR(soc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) kfree(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #endif /* CONFIG_SOC_BUS */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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