Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Helper module for board specific I2C bus registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2009 Nokia Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "omap_hwmod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "omap_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* In register I2C_CON, Bit 15 is the I2C enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define I2C_EN					BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OMAP2_I2C_CON_OFFSET			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP4_I2C_CON_OFFSET			0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_OMAP_I2C_HWMOD_NAME_LEN	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * omap_i2c_reset - reset the omap i2c module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * @oh: struct omap_hwmod *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * The i2c moudle in omap2, omap3 had a special sequence to reset. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * sequence is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * - Disable the I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * - Write to SOFTRESET bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * - Enable the I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * - Poll on the RESETDONE bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * The sequence is implemented in below function. This is called for 2420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * 2430 and omap3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int omap_i2c_reset(struct omap_hwmod *oh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u16 i2c_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	int c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		i2c_con = OMAP2_I2C_CON_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		i2c_con = OMAP4_I2C_CON_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	/* Disable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	v = omap_hwmod_read(oh, i2c_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	v &= ~I2C_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	omap_hwmod_write(v, oh, i2c_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* Write to the SOFTRESET bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	omap_hwmod_softreset(oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* Enable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	v = omap_hwmod_read(oh, i2c_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	v |= I2C_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	omap_hwmod_write(v, oh, i2c_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	/* Poll on RESETDONE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	omap_test_timeout((omap_hwmod_read(oh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 				oh->class->sysc->syss_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 				& SYSS_RESETDONE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 				MAX_MODULE_SOFTRESET_WAIT, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if (c == MAX_MODULE_SOFTRESET_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		pr_warn("%s: %s: softreset failed (waited %d usec)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		pr_debug("%s: %s: softreset in %d usec\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			oh->name, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }