Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * IP block integration code for the HDQ1W/1-wire IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *     Avinash.H.M <avinashhm@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "omap_hwmod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "omap_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "hdq1w.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * omap_hdq1w_reset - reset the OMAP HDQ1W module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * @oh: struct omap_hwmod *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * OCP soft reset the HDQ1W IP block.  Section 20.6.1.4 "HDQ1W/1-Wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * Software Reset" of the OMAP34xx Technical Reference Manual Revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * ZR (SWPU223R) does not include the rather important fact that, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * the reset to succeed, the HDQ1W module's internal clock gate must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * programmed to allow the clock to propagate to the rest of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * module.  In this sense, it's rather similar to the I2C custom reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * function.  Returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int omap_hdq1w_reset(struct omap_hwmod *oh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	int c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	/* Write to the SOFTRESET bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	omap_hwmod_softreset(oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	/* Enable the module's internal clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	/* Poll on RESETDONE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	omap_test_timeout((omap_hwmod_read(oh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 					   oh->class->sysc->syss_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			   & SYSS_RESETDONE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			  MAX_MODULE_SOFTRESET_WAIT, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (c == MAX_MODULE_SOFTRESET_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		pr_warn("%s: %s: softreset failed (waited %d usec)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		pr_debug("%s: %s: softreset in %d usec\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			 oh->name, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }