Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP2+ DMA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2003 - 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Graphics DMA and LCD DMA graphics tranformations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * by Imre Deak <imre.deak@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Converted DMA library into platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *	- G, Manjunath Kondaiah <manjugk@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static const struct omap_dma_reg reg_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* Common register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Channel specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* OMAP4 specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static unsigned configure_dma_errata(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned errata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * Errata applicable for OMAP2430ES1.0 and all omap2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * I.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * Erratum ID: Not Available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * Inter Frame DMA buffering issue DMA will wrongly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * buffer elements if packing and bursting is enabled. This might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * result in data gets stalled in FIFO at the end of the block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * guarantee no data will stay in the DMA FIFO in case inter frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * buffering occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * II.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * Erratum ID: Not Available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * DMA may hang when several channels are used in parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * In the following configuration, DMA channel hanging can occur:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * a. Channel i, hardware synchronized, is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * b. Another channel (Channel x), software synchronized, is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * c. Channel i is disabled before end of transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * d. Channel i is reenabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 * e. Steps 1 to 4 are repeated a certain number of times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * f. A third channel (Channel y), software synchronized, is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * Channel x and Channel y may hang immediately after step 'f'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * Workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * For any channel used - make sure NextLCH_ID is set to the value j.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (cpu_is_omap2420() || (cpu_is_omap2430() &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				(omap_type() == OMAP2430_REV_ES1_0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * after a transaction error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * Workaround: SW should explicitely disable the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (cpu_class_is_omap2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		SET_DMA_ERRATA(DMA_ERRATA_i378);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * Erratum ID: i541: sDMA FIFO draining does not finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * If sDMA channel is disabled on the fly, sDMA enters standby even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * through FIFO Drain is still in progress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Workaround: Put sDMA in NoStandby more before a logical channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * disabled, then put it back to SmartStandby right after the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * finishes FIFO draining.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		SET_DMA_ERRATA(DMA_ERRATA_i541);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * Erratum ID: i88 : Special programming model needed to disable DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * before end of block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * Workaround: software must ensure that the DMA is configured in No
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (omap_type() == OMAP3430_REV_ES1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		SET_DMA_ERRATA(DMA_ERRATA_i88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * read before the DMA controller finished disabling the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	SET_DMA_ERRATA(DMA_ERRATA_3_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * Erratum ID: Not Available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * after secure sram context save and restore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * Work around: Hence we need to manually clear those IRQs to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * spurious interrupts. This affects only secure devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		SET_DMA_ERRATA(DMA_ROMCODE_BUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* external DMA requests when tusb6010 is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{ "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct omap_dma_dev_attr dma_attr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		    IS_CSSA_32 | IS_CDSA_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.lch_count = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct omap_system_dma_plat_info dma_plat_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.reg_map	= reg_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.channel_stride	= 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.dma_attr	= &dma_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* One time initializations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int __init omap2_system_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	dma_plat_info.errata = configure_dma_errata();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (soc_is_omap24xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* DMA slave map for drivers not yet converted to DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		dma_plat_info.slave_map = omap24xx_sdma_dt_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (!soc_is_omap242x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dma_attr.dev_caps |= IS_RW_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) omap_arch_initcall(omap2_system_dma_init);