Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * OMAP2plus display device setup / initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	Senthilvadivu Guruswamy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	Sumit Semwal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/platform_data/omapdss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "omap_hwmod.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "omap_device.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include "display.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include "prm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DISPC_CONTROL		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DISPC_CONTROL2		0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DISPC_CONTROL3		0x0848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DISPC_IRQSTATUS		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DSS_CONTROL		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DSS_SDI_CONTROL		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DSS_PLL_CONTROL		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LCD_EN_MASK		(0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DIGIT_EN_MASK		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define FRAMEDONE_IRQ_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EVSYNC_EVEN_IRQ_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EVSYNC_ODD_IRQ_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define FRAMEDONE2_IRQ_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define FRAMEDONE3_IRQ_SHIFT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define FRAMEDONETV_IRQ_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *     reset before deciding that something has gone wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define FRAMEDONE_IRQ_TIMEOUT		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #if defined(CONFIG_FB_OMAP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static struct platform_device omap_display_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.name          = "omapdss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.id            = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.dev            = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.platform_data = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OMAP4_DSIPHY_SYSCON_OFFSET		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct regmap *omap4_dsi_mux_syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 enable_mask, enable_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 pipd_mask, pipd_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (dsi_id == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		pipd_mask = OMAP4_DSI1_PIPD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	} else if (dsi_id == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		pipd_mask = OMAP4_DSI2_PIPD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ret = regmap_read(omap4_dsi_mux_syscon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 					  OMAP4_DSIPHY_SYSCON_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 					  &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	reg &= ~enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	reg &= ~pipd_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	reg |= (lanes << enable_shift) & enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	reg |= (lanes << pipd_shift) & pipd_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return omap4_dsi_mux_pads(dsi_id, lane_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		omap4_dsi_mux_pads(dsi_id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static enum omapdss_version __init omap_display_get_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (cpu_is_omap24xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return OMAPDSS_VER_OMAP24xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else if (cpu_is_omap3630())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return OMAPDSS_VER_OMAP3630;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	else if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		if (soc_is_am35xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			return OMAPDSS_VER_AM35xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			if (omap_rev() < OMAP3430_REV_ES3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				return OMAPDSS_VER_OMAP34xx_ES1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				return OMAPDSS_VER_OMAP34xx_ES3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	} else if (omap_rev() == OMAP4430_REV_ES1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return OMAPDSS_VER_OMAP4430_ES1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			omap_rev() == OMAP4430_REV_ES2_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			omap_rev() == OMAP4430_REV_ES2_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return OMAPDSS_VER_OMAP4430_ES2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	else if (cpu_is_omap44xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return OMAPDSS_VER_OMAP4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	else if (soc_is_omap54xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return OMAPDSS_VER_OMAP5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	else if (soc_is_am43xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return OMAPDSS_VER_AM43xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	else if (soc_is_dra7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return OMAPDSS_VER_DRA7xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return OMAPDSS_VER_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int __init omapdss_init_fbdev(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	static struct omap_dss_board_info board_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.dsi_enable_pads = omap_dsi_enable_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.dsi_disable_pads = omap_dsi_disable_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	board_data.version = omap_display_get_version();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (board_data.version == OMAPDSS_VER_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		pr_err("DSS not supported on this SoC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	omap_display_device.dev.platform_data = &board_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	r = platform_device_register(&omap_display_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		pr_err("Unable to register omapdss device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* create vrfb device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	r = omap_init_vrfb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		pr_err("Unable to register omapvrfb device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* create FB device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	r = omap_init_fb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		pr_err("Unable to register omapfb device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* create V4L2 display device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	r = omap_init_vout();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		pr_err("Unable to register omap_vout device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* add DSI info for omap4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	node = of_find_node_by_name(NULL, "omap4_padconf_global");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const char * const omapdss_compat_names[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	"ti,omap2-dss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	"ti,omap3-dss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	"ti,omap4-dss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	"ti,omap5-dss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	"ti,dra7-dss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct device_node * __init omapdss_find_dss_of_node(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		node = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			omapdss_compat_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			return node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int __init omapdss_init_of(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* only create dss helper devices if dss is enabled in the .dts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	node = omapdss_find_dss_of_node();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (!of_device_is_available(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	pdev = of_find_device_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		pr_err("Unable to find DSS platform device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	put_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		pr_err("Unable to populate DSS submodule devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return omapdss_init_fbdev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) omap_device_initcall(omapdss_init_of);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif /* CONFIG_FB_OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void dispc_disable_outputs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	u32 v, irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct omap_dss_dispc_dev_attr *da;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct omap_hwmod *oh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	oh = omap_hwmod_lookup("dss_dispc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (!oh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (!oh->dev_attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* store value of LCDENABLE and DIGITENABLE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	v = omap_hwmod_read(oh, DISPC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	lcd_en = v & LCD_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	digit_en = v & DIGIT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* store value of LCDENABLE for LCD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (da->manager_count > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		v = omap_hwmod_read(oh, DISPC_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		lcd2_en = v & LCD_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	/* store value of LCDENABLE for LCD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (da->manager_count > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		v = omap_hwmod_read(oh, DISPC_CONTROL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		lcd3_en = v & LCD_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return; /* no managers currently enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	 * If any manager was enabled, we need to disable it before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 * DSS clocks are disabled or DISPC module is reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (lcd_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (digit_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		if (da->has_framedonetv_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				1 << EVSYNC_ODD_IRQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (lcd2_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (lcd3_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * clear any previous FRAMEDONE, FRAMEDONETV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	/* disable LCD and TV managers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	v = omap_hwmod_read(oh, DISPC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	omap_hwmod_write(v, oh, DISPC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	/* disable LCD2 manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (da->manager_count > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		v = omap_hwmod_read(oh, DISPC_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		v &= ~LCD_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		omap_hwmod_write(v, oh, DISPC_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	/* disable LCD3 manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (da->manager_count > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		v = omap_hwmod_read(oh, DISPC_CONTROL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		v &= ~LCD_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		omap_hwmod_write(v, oh, DISPC_CONTROL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	       irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		if (i > FRAMEDONE_IRQ_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int omap_dss_reset(struct omap_hwmod *oh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct omap_hwmod_opt_clk *oc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	int c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	int i, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		pr_err("dss_core: hwmod data doesn't contain reset data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		if (oc->_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			clk_prepare_enable(oc->_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	dispc_disable_outputs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	/* clear SDI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (cpu_is_omap3430()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 * clear DSS_CONTROL register to switch DSS clock sources to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	 * PRCM clock, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	omap_hwmod_write(0x0, oh, DSS_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 				& SYSS_RESETDONE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			MAX_MODULE_SOFTRESET_WAIT, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (c == MAX_MODULE_SOFTRESET_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		pr_warn("dss_core: waiting for reset to finish failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		pr_debug("dss_core: softreset done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		if (oc->_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			clk_disable_unprepare(oc->_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }