Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-omap2/cpuidle34xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * OMAP3 CPU IDLE Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2008 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Rajendra Nayak <rnayak@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2007 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Karthik Dasu <karthik-dp@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 2006 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Copyright (C) 2005 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Based on pm.c for omap2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "powerdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Mach specific information to be recorded in the C-state driver_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct omap3_idle_statedata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u8 mpu_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 core_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8 per_min_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * Possible flag bits for struct omap3_idle_statedata.flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *    inactive.  This in turn prevents the MPU DPLL from entering autoidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *    mode, so wakeup latency is greatly reduced, at the cost of additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *    energy consumption.  This also prevents the CORE clockdomain from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *    entering idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * Prevent PER OFF if CORE is not in RETention or OFF as this would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * disable PER wakeups completely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct omap3_idle_statedata omap3_idle_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.mpu_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.core_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		/* In C1 do not allow PER state lower than CORE state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.per_min_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.mpu_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.core_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.per_min_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.mpu_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.core_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.per_min_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.mpu_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.core_state = PWRDM_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.per_min_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.mpu_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.core_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.per_min_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.mpu_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.core_state = PWRDM_POWER_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.per_min_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.mpu_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.core_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.per_min_state = PWRDM_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * omap3_enter_idle - Programs OMAP3 to enter the specified state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * @dev: cpuidle device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * @drv: cpuidle driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * @index: the index of state to be entered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int omap3_enter_idle(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			    struct cpuidle_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			    int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (omap_irq_pending() || need_resched())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		goto return_sleep_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* Deny idle for C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		pwrdm_set_next_pwrst(core_pd, cx->core_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * Call idle CPU PM enter notifier chain so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * VFP context is saved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (cx->mpu_state == PWRDM_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		error = cpu_pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			goto out_clkdm_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* Execute ARM wfi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	omap_sram_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * Call idle CPU PM enter notifier chain to restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * VFP context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (cx->mpu_state == PWRDM_POWER_OFF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	    pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		cpu_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) out_clkdm_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Re-allow idle for C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return_sleep_time:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * next_valid_state - Find next valid C-state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * @dev: cpuidle device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * @drv: cpuidle driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * @index: Index of currently selected c-state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * If the state corresponding to index is valid, index is returned back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * to the caller. Else, this function searches for a lower c-state which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * still valid (as defined in omap3_power_states[]) and returns its index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * A state is valid if the 'valid' field is enabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * if it satisfies the enable_off_mode condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int next_valid_state(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			    struct cpuidle_driver *drv, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 mpu_deepest_state = PWRDM_POWER_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 core_deepest_state = PWRDM_POWER_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int next_index = 0; /* C1 is the default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (enable_off_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		mpu_deepest_state = PWRDM_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		 * CORE OFF mode is not supported in a stable form, restrict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		 * instead the CORE state to RET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			core_deepest_state = PWRDM_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Check if current state is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if ((cx->mpu_state >= mpu_deepest_state) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	    (cx->core_state >= core_deepest_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * Drop to next valid state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * Start search from the next (lower) state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	for (idx = index - 1; idx >= 0; idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		cx = &omap3_idle_data[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if ((cx->mpu_state >= mpu_deepest_state) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		    (cx->core_state >= core_deepest_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			next_index = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return next_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * omap3_enter_idle_bm - Checks for any bus activity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * @dev: cpuidle device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * @drv: cpuidle driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * @index: array index of target state to be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * This function checks for any pending activity and then programs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * the device to the specified or a safer state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int omap3_enter_idle_bm(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			       struct cpuidle_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			       int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int new_state_idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u8 per_next_state, per_saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct omap3_idle_statedata *cx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * Use only C1 if CAM is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * CAM does not have wakeup capability in OMAP3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		new_state_idx = drv->safe_state_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		new_state_idx = next_valid_state(dev, drv, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * FIXME: we currently manage device-specific idle states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 *        for PER and CORE in combination with CPU-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 *        idle states.  This is wrong, and device-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 *        idle management needs to be separated out into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 *        its own code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* Program PER state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	cx = &omap3_idle_data[new_state_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	per_next_state = pwrdm_read_next_pwrst(per_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	per_saved_state = per_next_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (per_next_state < cx->per_min_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		per_next_state = cx->per_min_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		pwrdm_set_next_pwrst(per_pd, per_next_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ret = omap3_enter_idle(dev, drv, new_state_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Restore original PER state if it was modified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (per_next_state != per_saved_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		pwrdm_set_next_pwrst(per_pd, per_saved_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct cpuidle_driver omap3_idle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.name             = "omap3_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.owner            = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.states = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			.exit_latency	  = 2 + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			.target_residency = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			.name		  = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			.desc		  = "MPU ON + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			.exit_latency	  = 10 + 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			.target_residency = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			.name		  = "C2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			.desc		  = "MPU ON + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			.exit_latency	  = 50 + 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			.target_residency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			.name		  = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			.desc		  = "MPU RET + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			.exit_latency	  = 1500 + 1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			.target_residency = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			.name		  = "C4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			.desc		  = "MPU OFF + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			.exit_latency	  = 2500 + 7500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			.target_residency = 12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			.name		  = "C5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			.desc		  = "MPU RET + CORE RET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			.exit_latency	  = 3000 + 8500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			.target_residency = 15000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			.name		  = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			.desc		  = "MPU OFF + CORE RET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			.exit_latency	  = 10000 + 30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			.target_residency = 30000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			.name		  = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			.desc		  = "MPU OFF + CORE OFF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.state_count = ARRAY_SIZE(omap3_idle_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.safe_state_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  * Numbers based on measurements made in October 2009 for PM optimized kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  * and worst case latencies).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct cpuidle_driver omap3430_idle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.name             = "omap3430_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.owner            = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.states = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			.exit_latency	  = 110 + 162,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			.target_residency = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			.name		  = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			.desc		  = "MPU ON + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			.exit_latency	  = 106 + 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			.target_residency = 309,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			.name		  = "C2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			.desc		  = "MPU ON + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			.exit_latency	  = 107 + 410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			.target_residency = 46057,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			.name		  = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			.desc		  = "MPU RET + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			.exit_latency	  = 121 + 3374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			.target_residency = 46057,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			.name		  = "C4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			.desc		  = "MPU OFF + CORE ON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			.exit_latency	  = 855 + 1146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			.target_residency = 46057,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			.name		  = "C5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			.desc		  = "MPU RET + CORE RET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			.exit_latency	  = 7580 + 4134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			.target_residency = 484329,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			.name		  = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			.desc		  = "MPU OFF + CORE RET",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			.enter		  = omap3_enter_idle_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			.exit_latency	  = 7505 + 15274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			.target_residency = 484329,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			.name		  = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			.desc		  = "MPU OFF + CORE OFF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.state_count = ARRAY_SIZE(omap3_idle_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.safe_state_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Public functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)  * omap3_idle_init - Init routine for OMAP3 idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)  * Registers the OMAP3 specific cpuidle driver to the cpuidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)  * framework with the valid set of states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int __init omap3_idle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	mpu_pd = pwrdm_lookup("mpu_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	core_pd = pwrdm_lookup("core_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	per_pd = pwrdm_lookup("per_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	cam_pd = pwrdm_lookup("cam_pwrdm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (cpu_is_omap3430())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		return cpuidle_register(&omap3430_idle_driver, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		return cpuidle_register(&omap3_idle_driver, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }