^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-omap2/control.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * OMAP2/3/4 System Control Module definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007-2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2007-2008, 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Written by Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "am33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP242X_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP243X_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP343X_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AM33XX_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP242X_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP243X_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP343X_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AM33XX_CTRL_REGADDR(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * OMAP24XX and OMAP34XX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Control submodule offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP2_CONTROL_INTERFACE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP2_CONTROL_PADCONFS 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP2_CONTROL_GENERAL 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP343X_CONTROL_MEM_WKUP 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* TI81XX spefic control submodules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TI81XX_CONTROL_DEVBOOT 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TI81XX_CONTROL_DEVCONF 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 242x-only CONTROL_GENERAL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* 243x-only CONTROL_GENERAL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 24xx-only CONTROL_GENERAL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* 34xx-only CONTROL_GENERAL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* OMAP3630 only CONTROL_GENERAL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* OMAP44xx control efuse offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB 0x24C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* AM35XX only CONTROL_GENERAL register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 34xx PADCONF register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (i)*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* 34xx GENERAL_WKUP register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP34XX_CONTROL_WKUP_CTRL (OMAP343X_CONTROL_GENERAL_WKUP - 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OMAP36XX_GPIO_IO_PWRDNZ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x008 + (i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* 36xx-only RTA - Retention till Access control registers and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OMAP36XX_RTA_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* 34xx D2D idle-related pins, handled by PM core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* TI81XX CONTROL_DEVBOOT register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TI81XX_CONTROL_STATUS (TI81XX_CONTROL_DEVBOOT + 0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* TI81XX CONTROL_DEVCONF register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* OMAP4 CONTROL MODULE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* OMAP4 CONTROL_DSIPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP4_DSI2_LANEENABLE_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OMAP4_DSI1_LANEENABLE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OMAP4_DSI1_PIPD_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OMAP4_DSI2_PIPD_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* OMAP4 CONTROL_CAMERA_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* OMAP54XX CONTROL STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define OMAP5XXX_CONTROL_STATUS 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP5_DEVICETYPE_MASK (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* DRA7XX CONTROL CORE BOOTSTRAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRA7_SPEEDSELECT_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * REVISIT: This list of registers is not comprehensive - there are more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * that should be added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Control module register bit defines - these should eventually go into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * their own regbits file. Some of these will be complicated, depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * on the device type (general-purpose, emulator, test, secure, bad, other)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * and the security mode (secure, non-secure, don't care)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* CONTROL_DEVCONF0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define OMAP24XX_USBSTANDBYCTRL (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OMAP2_MCBSP1_FSR_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OMAP2_MCBSP1_CLKR_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* CONTROL_DEVCONF1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* CONTROL_STATUS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OMAP2_DEVICETYPE_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP2_SYSBOOT_5_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OMAP2_SYSBOOT_4_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OMAP2_SYSBOOT_3_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OMAP2_SYSBOOT_2_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define OMAP2_SYSBOOT_1_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define OMAP2_SYSBOOT_0_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* CONTROL_PBIAS_LITE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OMAP343X_PBIASLITEVMODE1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OMAP2_PBIASLITEVMODE0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* CONTROL_PROG_IO1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* CONTROL_IVA2_BOOTMOD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OMAP3_IVA2_BOOTMOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* CONTROL_PADCONF_X bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) OMAP343X_SCRATCHPAD + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define AM35XX_HECC_VBUSP_CLK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define AM35XX_USBOTG_FCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define AM35XX_CPGMAC_FCLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define AM35XX_VPFE_FCLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* AM35XX CONTROL_LVL_INTR_CLEAR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define AM35XX_USBOTGSS_INT_CLR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* AM35XX CONTROL_IP_SW_RESET bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define AM35XX_USBOTGSS_SW_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define AM35XX_CPGMACSS_SW_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define AM35XX_HECC_SW_RST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define AM35XX_VPFE_PCLK_SW_RST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* AM33XX CONTROL_STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define AM33XX_CONTROL_STATUS 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* AM33XX CONTROL_STATUS bitfields (partial) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* AM33XX PWMSS Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* AM33XX PWMSS Control bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define AM33XX_PWMSS0_TBCLKEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* DEV Feature register to identify AM33XX features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define AM33XX_DEV_FEATURE 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define AM33XX_SGX_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Additional AM33XX/AM43XX CONTROL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define AM33XX_CONTROL_SYSCONFIG_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define AM33XX_CONTROL_STATUS_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET 0x041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET 0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET 0x042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET 0x0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET 0x0448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET 0x044c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET 0x0458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define AM33XX_CONTROL_MOSC_CTRL_OFFSET 0x0468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define AM33XX_CONTROL_RCOSC_CTRL_OFFSET 0x046c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET 0x0470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET 0x0534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET 0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define AM33XX_CONTROL_MMU_CFG_OFFSET 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define AM33XX_CONTROL_TPTC_CFG_OFFSET 0x0614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define AM33XX_CONTROL_USB_CTRL0_OFFSET 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define AM33XX_CONTROL_USB_CTRL1_OFFSET 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET 0x0648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define AM43XX_CONTROL_USB_CTRL2_OFFSET 0x064c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define AM43XX_CONTROL_GMII_SEL_OFFSET 0x0650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define AM43XX_CONTROL_MPUSS_CTRL_OFFSET 0x0654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET 0x0658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define AM43XX_CONTROL_PWMSS_CTRL_OFFSET 0x0664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define AM33XX_CONTROL_MREQPRIO_0_OFFSET 0x0670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define AM33XX_CONTROL_MREQPRIO_1_OFFSET 0x0674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET 0x0690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET 0x0694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET 0x0698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET 0x069c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define AM33XX_CONTROL_SMRT_CTRL_OFFSET 0x06a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET 0x06a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define AM43XX_CONTROL_CQDETECT_STS_OFFSET 0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define AM43XX_CONTROL_CQDETECT_STS2_OFFSET 0x0e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define AM43XX_CONTROL_VTP_CTRL_OFFSET 0x0e0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define AM33XX_CONTROL_VREF_CTRL_OFFSET 0x0e14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET 0x0f90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET 0x0f94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET 0x0f98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET 0x0f9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET 0x0fa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET 0x0fa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET 0x0fa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET 0x0fac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET 0x0fb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET 0x0fb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET 0x0fb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET 0x0fbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET 0x0fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET 0x0fc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET 0x0fc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET 0x0fcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET 0x0fd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET 0x0fd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET 0x0fd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET 0x0fdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define AM33XX_CONTROL_RESET_ISO_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* CONTROL OMAP STATUS register to identify OMAP3 features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define OMAP3_CONTROL_OMAP_STATUS 0x044c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define OMAP3_SGX_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define FEAT_SGX_FULL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define FEAT_SGX_HALF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define FEAT_SGX_NONE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define OMAP3_IVA_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define FEAT_IVA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define FEAT_IVA_NONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define OMAP3_L2CACHE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define FEAT_L2CACHE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FEAT_L2CACHE_64KB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FEAT_L2CACHE_128KB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define FEAT_L2CACHE_256KB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define OMAP3_ISP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define FEAT_ISP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define FEAT_ISP_NONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define OMAP3_NEON_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define FEAT_NEON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define FEAT_NEON_NONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #ifdef CONFIG_ARCH_OMAP2PLUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) extern u8 omap_ctrl_readb(u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) extern u16 omap_ctrl_readw(u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) extern u32 omap_ctrl_readl(u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) extern void omap_ctrl_writeb(u8 val, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) extern void omap_ctrl_writew(u16 val, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) extern void omap_ctrl_writel(u32 val, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) extern void omap3_save_scratchpad_contents(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) extern void omap3_clear_scratchpad_contents(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) extern void omap3_restore(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) extern void omap3_restore_es3(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) extern void omap3_restore_3630(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) extern u32 omap3_arm_context[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) extern void omap3_control_save_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) extern void omap3_control_restore_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) extern void omap3_ctrl_write_boot_mode(u8 bootmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) extern void omap3630_ctrl_disable_rta(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) extern int omap3_ctrl_save_padconf(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) void omap3_ctrl_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int omap2_control_base_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int omap_control_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) void omap2_set_globals_control(void __iomem *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void __init omap3_control_legacy_iomap_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define omap_ctrl_readb(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define omap_ctrl_readw(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define omap_ctrl_readl(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define omap4_ctrl_pad_readl(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define omap_ctrl_writeb(x, y) WARN_ON(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define omap_ctrl_writew(x, y) WARN_ON(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define omap_ctrl_writel(x, y) WARN_ON(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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