^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3 System Control Module register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Written by Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "prm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "prm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "cm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "sdrc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "control.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Used by omap3_ctrl_save_padconf() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define START_PADCONF_SAVE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PADCONF_SAVE_DONE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void __iomem *omap2_ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static s16 omap2_ctrl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct omap3_scratchpad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 boot_config_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 public_restore_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 secure_ram_restore_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 sdrc_module_semaphore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 prcm_block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 sdrc_block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct omap3_scratchpad_prcm_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 prm_contents[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 cm_contents[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 prcm_block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct omap3_scratchpad_sdrc_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 cs_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 sharing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 err_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 dll_a_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 dll_b_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 cs_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 mcfg_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 mr_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 emr_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 emr_2_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 emr_3_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 actim_ctrla_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 actim_ctrlb_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 rfr_ctrl_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 cs_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 mcfg_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 mr_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 emr_1_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 emr_2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u16 emr_3_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 actim_ctrla_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 actim_ctrlb_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 rfr_ctrl_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 dcdl_1_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 dcdl_2_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void *omap3_secure_ram_storage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * This is used to store ARM registers in SDRAM before attempting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * an MPU OFF. The save and restore happens from the SRAM sleep code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * The address is stored in scratchpad, so that it can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * during the restore path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 omap3_arm_context[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct omap3_control_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 devconf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 mem_dftrw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 mem_dftrw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 msuspendmux_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 msuspendmux_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 msuspendmux_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 msuspendmux_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 msuspendmux_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 msuspendmux_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 sec_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 devconf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 csirxfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 iva2_bootaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 iva2_bootmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 wkup_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 debobs_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 debobs_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 debobs_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 debobs_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 debobs_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 debobs_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 debobs_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 debobs_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 debobs_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 prog_io0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 prog_io1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 dss_dpll_spreading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 core_dpll_spreading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 per_dpll_spreading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 usbhost_dpll_spreading;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 pbias_lite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 temp_sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 sramldo4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 sramldo5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 padconf_sys_nirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct omap3_control_regs control_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __init omap2_set_globals_control(void __iomem *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) omap2_ctrl_base = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 omap_ctrl_readb(u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 byte_offset = offset & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = omap_ctrl_readl(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return (val >> (byte_offset * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 omap_ctrl_readw(u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 byte_offset = offset & 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = omap_ctrl_readl(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return (val >> (byte_offset * 8)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 omap_ctrl_readl(u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) offset &= 0xfffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return readl_relaxed(omap2_ctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void omap_ctrl_writeb(u8 val, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 byte_offset = offset & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tmp = omap_ctrl_readl(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tmp |= val << (byte_offset * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) omap_ctrl_writel(tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void omap_ctrl_writew(u16 val, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 byte_offset = offset & 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tmp = omap_ctrl_readl(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tmp |= val << (byte_offset * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) omap_ctrl_writel(tmp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void omap_ctrl_writel(u32 val, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) offset &= 0xfffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(val, omap2_ctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @bootmode: 8-bit value to pass to some boot code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Set the bootmode in the scratchpad RAM. This is used after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * system restarts. Not sure what actually uses this - it may be the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * bootloader, rather than the boot ROM - contrary to the preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * comment below. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void omap3_ctrl_write_boot_mode(u8 bootmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) l = ('B' << 24) | ('M' << 16) | bootmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Reserve the first word in scratchpad for communicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * with the boot ROM. A pointer to a data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * describing the boot process can be stored there,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * cf. OMAP34xx TRM, Initialization / Software Booting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * XXX This should use some omap_ctrl_writel()-type function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @bootaddr: physical address of the boot loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Set boot address for the boot loader of a supported processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * when a power ON sequence occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_err("%s: unsupported omap type\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) omap_ctrl_writel(bootaddr, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @bootmode: 8-bit value to pass to some boot code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Sets boot mode for the boot loader of a supported processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * when a power ON sequence occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pr_err("%s: unsupported omap type\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) omap_ctrl_writel(bootmode, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Clears the scratchpad contents in case of cold boot-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * called during bootup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void omap3_clear_scratchpad_contents(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void __iomem *v_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (omap3xxx_prm_clear_global_cold_reset()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for ( ; offset <= max_offset; offset += 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel_relaxed(0x0, (v_addr + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Populate the scratchpad structure with restore structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void omap3_save_scratchpad_contents(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *scratchpad_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 arm_context_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct omap3_scratchpad scratchpad_contents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct omap3_scratchpad_prcm_block prcm_block_contents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct omap3_scratchpad_sdrc_block sdrc_block_contents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Populate the Scratchpad contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * The "get_*restore_pointer" functions are used to provide a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * physical restore address where the ROM code jumps while waking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * up from MPU OFF/OSWR state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * The restore pointer is stored into the scratchpad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) scratchpad_contents.boot_config_ptr = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (cpu_is_omap3630())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) scratchpad_contents.public_restore_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __pa_symbol(omap3_restore_3630);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else if (omap_rev() != OMAP3430_REV_ES3_0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) omap_rev() != OMAP3430_REV_ES3_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) omap_rev() != OMAP3430_REV_ES3_1_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) scratchpad_contents.public_restore_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __pa_symbol(omap3_restore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) scratchpad_contents.public_restore_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __pa_symbol(omap3_restore_es3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (omap_type() == OMAP2_DEVICE_TYPE_GP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) scratchpad_contents.secure_ram_restore_ptr = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) scratchpad_contents.secure_ram_restore_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (u32) __pa(omap3_secure_ram_storage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) scratchpad_contents.sdrc_module_semaphore = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) scratchpad_contents.prcm_block_offset = 0x2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) scratchpad_contents.sdrc_block_offset = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Populate the PRCM block contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) prcm_block_contents.prcm_block_size = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Populate the SDRC block contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sdrc_block_contents.sysconfig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sdrc_block_contents.cs_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sdrc_block_contents.sharing =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sdrc_block_contents.err_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) sdrc_block_contents.dll_b_ctrl = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * be programed to issue automatic self refresh on timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * of AUTO_CNT = 1 prior to any transition to OFF mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) && (omap_rev() >= OMAP3430_REV_ES3_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ~(SDRC_POWER_AUTOCOUNT_MASK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SDRC_POWER_CLKCTRL_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SDRC_SELF_REFRESH_ON_AUTOCOUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sdrc_block_contents.cs_0 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sdrc_block_contents.emr_1_0 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) sdrc_block_contents.emr_2_0 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sdrc_block_contents.emr_3_0 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) sdrc_block_contents.actim_ctrla_0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sdrc_block_contents.actim_ctrlb_0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sdrc_block_contents.rfr_ctrl_0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sdrc_read_reg(SDRC_RFR_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sdrc_block_contents.cs_1 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sdrc_block_contents.emr_1_1 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sdrc_block_contents.emr_2_1 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sdrc_block_contents.emr_3_1 = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sdrc_block_contents.actim_ctrla_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sdrc_block_contents.actim_ctrlb_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sdrc_block_contents.rfr_ctrl_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sdrc_read_reg(SDRC_RFR_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sdrc_block_contents.dcdl_1_ctrl = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sdrc_block_contents.dcdl_2_ctrl = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sdrc_block_contents.flags = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sdrc_block_contents.block_size = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) arm_context_addr = __pa_symbol(omap3_arm_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Copy all the contents to the scratchpad location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) memcpy_toio(scratchpad_address, &scratchpad_contents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sizeof(scratchpad_contents));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Scratchpad contents being 32 bits, a divide by 4 done here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) memcpy_toio(scratchpad_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) scratchpad_contents.prcm_block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &prcm_block_contents, sizeof(prcm_block_contents));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) memcpy_toio(scratchpad_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) scratchpad_contents.sdrc_block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &sdrc_block_contents, sizeof(sdrc_block_contents));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Copies the address of the location in SDRAM where ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * registers get saved during a MPU OFF transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) memcpy_toio(scratchpad_address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) scratchpad_contents.sdrc_block_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sizeof(sdrc_block_contents), &arm_context_addr, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void omap3_control_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) control_context.mem_dftrw0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) control_context.mem_dftrw1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) control_context.msuspendmux_0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) control_context.msuspendmux_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) control_context.msuspendmux_2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) control_context.msuspendmux_3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) control_context.msuspendmux_4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) control_context.msuspendmux_5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) control_context.iva2_bootaddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) control_context.iva2_bootmod =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) control_context.dss_dpll_spreading =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) control_context.core_dpll_spreading =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) control_context.per_dpll_spreading =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) control_context.usbhost_dpll_spreading =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) control_context.pbias_lite =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) control_context.temp_sensor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) control_context.padconf_sys_nirq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) void omap3_control_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) omap_ctrl_writel(control_context.mem_dftrw0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) OMAP343X_CONTROL_MEM_DFTRW0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) omap_ctrl_writel(control_context.mem_dftrw1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) OMAP343X_CONTROL_MEM_DFTRW1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) omap_ctrl_writel(control_context.msuspendmux_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) OMAP2_CONTROL_MSUSPENDMUX_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) omap_ctrl_writel(control_context.msuspendmux_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) OMAP2_CONTROL_MSUSPENDMUX_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) omap_ctrl_writel(control_context.msuspendmux_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) OMAP2_CONTROL_MSUSPENDMUX_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) omap_ctrl_writel(control_context.msuspendmux_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) OMAP2_CONTROL_MSUSPENDMUX_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) omap_ctrl_writel(control_context.msuspendmux_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) OMAP2_CONTROL_MSUSPENDMUX_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) omap_ctrl_writel(control_context.msuspendmux_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) OMAP2_CONTROL_MSUSPENDMUX_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) omap_ctrl_writel(control_context.iva2_bootaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) OMAP343X_CONTROL_IVA2_BOOTADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) omap_ctrl_writel(control_context.iva2_bootmod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) OMAP343X_CONTROL_IVA2_BOOTMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) omap_ctrl_writel(control_context.dss_dpll_spreading,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) OMAP343X_CONTROL_DSS_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) omap_ctrl_writel(control_context.core_dpll_spreading,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) OMAP343X_CONTROL_CORE_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) omap_ctrl_writel(control_context.per_dpll_spreading,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) OMAP343X_CONTROL_PER_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) omap_ctrl_writel(control_context.usbhost_dpll_spreading,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) omap_ctrl_writel(control_context.pbias_lite,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) OMAP343X_CONTROL_PBIAS_LITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) omap_ctrl_writel(control_context.temp_sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) OMAP343X_CONTROL_TEMP_SENSOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) omap_ctrl_writel(control_context.padconf_sys_nirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) OMAP343X_CONTROL_PADCONF_SYSNIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) void omap3630_ctrl_disable_rta(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!cpu_is_omap3630())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Tell the SCM to start saving the padconf registers, then wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * the process to complete. Returns 0 unconditionally, although it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * should also eventually be able to return -ETIMEDOUT, if the save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * does not complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * XXX This function is missing a timeout. What should it be?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int omap3_ctrl_save_padconf(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 cpo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Save the padconf registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cpo |= START_PADCONF_SAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* wait for the save to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) & PADCONF_SAVE_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * force disable IVA2 so that it does not prevent any low-power states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void __init omap3_ctrl_set_iva_bootmode_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) OMAP343X_CONTROL_IVA2_BOOTMOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Sets up the pads controlling the stacked modem in such way that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * device can enter idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void __init omap3_ctrl_setup_d2d_padconf(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u16 mask, padconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * In a stand alone OMAP3430 where there is not a stacked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * modem for the D2D Idle Ack and D2D MStandby must be pulled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) padconf |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) padconf |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * omap3_ctrl_init - does static initializations for control module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Initializes system control module. This sets up the sysconfig autoidle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * and sets up modem and iva2 so that they can be idled properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) void __init omap3_ctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) omap3_ctrl_set_iva_bootmode_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) omap3_ctrl_setup_d2d_padconf();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static unsigned long am43xx_control_reg_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) AM33XX_CONTROL_SYSCONFIG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) AM33XX_CONTROL_STATUS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) AM43XX_CONTROL_MPU_L2_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) AM33XX_CONTROL_BANDGAP_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) AM33XX_CONTROL_BANDGAP_TRIM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) AM33XX_CONTROL_MOSC_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) AM33XX_CONTROL_TPTC_CFG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) AM33XX_CONTROL_USB_CTRL0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) AM33XX_CONTROL_USB_CTRL1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) AM43XX_CONTROL_USB_CTRL2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) AM43XX_CONTROL_GMII_SEL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) AM43XX_CONTROL_MPUSS_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) AM43XX_CONTROL_PWMSS_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) AM33XX_CONTROL_MREQPRIO_0_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) AM33XX_CONTROL_MREQPRIO_1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) AM33XX_CONTROL_SMRT_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) AM43XX_CONTROL_CQDETECT_STS_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) AM43XX_CONTROL_CQDETECT_STS2_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) AM43XX_CONTROL_VTP_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) AM33XX_CONTROL_VREF_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) AM33XX_CONTROL_RESET_ISO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * am43xx_control_save_context - Save the wakeup domain registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Save the wkup domain registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void am43xx_control_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) am33xx_control_vals[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) omap_ctrl_readl(am43xx_control_reg_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * am43xx_control_restore_context - Restore the wakeup domain registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Restore the wkup domain registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void am43xx_control_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) omap_ctrl_writel(am33xx_control_vals[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) am43xx_control_reg_offsets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case CPU_CLUSTER_PM_ENTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (enable_off_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) am43xx_control_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case CPU_CLUSTER_PM_EXIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (enable_off_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) am43xx_control_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct control_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) s16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static struct control_init_data ctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .index = TI_CLKM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct control_init_data omap2_ctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .index = TI_CLKM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .offset = -OMAP2_CONTROL_GENERAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const struct control_init_data ctrl_aux_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .index = TI_CLKM_CTRL_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const struct of_device_id omap_scrm_dt_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { .compatible = "ti,am3-scm", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { .compatible = "ti,am4-scm", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { .compatible = "ti,dm814-scm", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * omap2_control_base_init - initialize iomappings for the control driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Detects and initializes the iomappings for the control driver, based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * on the DT data. Returns 0 in success, negative error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int __init omap2_control_base_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct control_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) data = (struct control_init_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mem = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (data->index == TI_CLKM_CTRL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) omap2_ctrl_base = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) omap2_ctrl_offset = data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) data->mem = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * omap_control_init - low level init for the control driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Initializes the low level clock infrastructure for control driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Returns 0 in success, negative error value in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int __init omap_control_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct device_node *np, *scm_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) const struct omap_prcm_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Check if we have scm_conf node, if yes, use this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * access clock registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) scm_conf = of_get_child_by_name(np, "scm_conf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (scm_conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) syscon = syscon_node_to_regmap(scm_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (IS_ERR(syscon))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return PTR_ERR(syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (of_get_child_by_name(scm_conf, "clocks")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = omap2_clk_provider_init(scm_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) data->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) syscon, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* No scm_conf found, direct access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = omap2_clk_provider_init(np, data->index, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) data->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (soc_is_am43xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) nb.notifier_call = cpu_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cpu_pm_register_notifier(&nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * Legacy iomap init for clock provider. Needed only by legacy boot mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * where the base addresses are not parsed from DT, but still required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * by the clock driver to be setup properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) void __init omap3_control_legacy_iomap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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