Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Header for code common to all OMAP2+ machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * You should have received a copy of the  GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * with this program; if not, write  to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/platform_data/i2c-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/irqchip/irq-omap-intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include "i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include "serial.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include "usb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OMAP_INTC_START		NR_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) extern int (*omap_pm_soc_init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) int omap_pm_nop_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) int omap2_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static inline int omap2_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) int omap3_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static inline int omap3_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) int omap4_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) int omap4_pm_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static inline int omap4_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static inline int omap4_pm_init_early(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #if defined(CONFIG_PM) && (defined(CONFIG_SOC_AM33XX) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	defined(CONFIG_SOC_AM43XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) int amx3_common_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static inline int amx3_common_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) extern void omap2_init_common_infrastructure(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) extern void omap_init_time(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) extern void omap3_secure_sync32k_timer_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) extern void omap3_gptimer_timer_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) extern void omap4_local_timer_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int omap_l2_cache_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP_L2C_AUX_CTRL	(L2C_AUX_CTRL_SHARED_OVERRIDE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				 L310_AUX_CTRL_DATA_PREFETCH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				 L310_AUX_CTRL_INSTR_PREFETCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void omap4_l2c310_write_sec(unsigned long val, unsigned reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline int omap_l2_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP_L2C_AUX_CTRL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define omap4_l2c310_write_sec	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern void omap5_realtime_timer_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline void omap5_realtime_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void omap2420_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void omap2430_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void omap3430_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void omap35xx_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void omap3630_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void omap3_init_early(void);	/* Do not use this one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void am33xx_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void am35xx_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void ti814x_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void ti816x_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void am33xx_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void am43xx_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void am43xx_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void omap4430_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void omap5_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void omap3_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void omap4430_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void omap2420_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void omap2430_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void ti81xx_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void am33xx_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void omap5_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int omap2_common_pm_late_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void dra7xx_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void dra7xx_init_late(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_SOC_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void omap_soc_device_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline void omap_soc_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_SOC_AM33XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void am33xx_restart(enum reboot_mode mode, const char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void ti81xx_restart(enum reboot_mode mode, const char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline void ti81xx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void omap44xx_restart(enum reboot_mode mode, const char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void omap_barrier_reserve_memblock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void omap_barriers_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline void omap_barrier_reserve_memblock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* This gets called from mach-omap2/io.c, do not call this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __init omap242x_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void __init omap243x_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void __init omap3_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void __init am33xx_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void __init omap4_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void __init omap5_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __init dra7xx_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void __init ti81xx_map_io(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * omap_test_timeout - busy-loop, testing a condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * @cond: condition to test until it evaluates to true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * @timeout: maximum number of microseconds in the timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * @index: loop index (integer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * Loop waiting for @cond to become true or until at least @timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * microseconds have passed.  To use, define some integer @index in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * calling code.  After running, if @index == @timeout, then the loop has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * timed out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define omap_test_timeout(cond, timeout, index)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ({								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (index = 0; index < timeout; index++) {		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		if (cond)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			break;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		udelay(1);					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) extern struct device *omap2_get_mpuss_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) extern struct device *omap2_get_iva_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) extern struct device *omap2_get_l3_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) extern struct device *omap4_get_dsp_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void omap_gic_of_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef CONFIG_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) extern void __iomem *omap4_get_l2cache_base(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) extern void __iomem *omap4_get_scu_base(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline void __iomem *omap4_get_scu_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) extern void gic_dist_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) extern void gic_dist_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) extern bool gic_dist_disabled(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) extern void gic_timer_retrigger(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) extern void _omap_smc1(u32 fn, u32 arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) extern void omap4_sar_ram_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) extern void __iomem *omap4_get_sar_ram_base(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) extern void omap4_mpuss_early_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) extern void omap_do_wfi(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Needed for secondary core boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) extern void omap_auxcoreboot_addr(u32 cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) extern u32 omap_read_auxcoreboot0(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) extern void omap4_cpu_die(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) extern int omap4_cpu_kill(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extern const struct smp_operations omap4_smp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) extern u32 omap4_get_cpu1_ns_pa_addr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #if defined(CONFIG_SMP) && defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) extern int omap4_mpuss_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline int omap4_enter_lowpower(unsigned int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					unsigned int power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline int omap4_mpuss_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void omap4_secondary_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void omap4460_secondary_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int omap4_finish_suspend(unsigned long cpu_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void omap4_cpu_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static inline void omap4_secondary_startup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static inline void omap4460_secondary_startup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline int omap4_finish_suspend(unsigned long cpu_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline void omap4_cpu_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void omap5_secondary_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void omap5_secondary_hyp_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static inline void omap5_secondary_startup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static inline void omap5_secondary_hyp_startup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) extern int dra7xx_pciess_reset(struct omap_hwmod *oh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static inline int dra7xx_pciess_reset(struct omap_hwmod *oh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct omap_system_dma_plat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void pdata_quirks_init(const struct of_device_id *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void omap_auxdata_legacy_init(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void omap_pcs_legacy_init(int irq, void (*rearm)(void));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) extern struct omap_system_dma_plat_info dma_plat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct omap_sdrc_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 				      struct omap_sdrc_params *sdrc_cs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) extern void omap_reserve(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct omap_hwmod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) extern int omap_dss_reset(struct omap_hwmod *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* SoC specific clock initializer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int omap_clk_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif /* __ASSEMBLER__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */