Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP2+ common Clock Management (CM) IP block functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * XXX This code should eventually be moved to a CM driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "cm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "cm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "cm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "cm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * cm_ll_data: function pointers to SoC-specific implementations of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * common CM functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct cm_ll_data null_cm_ll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static const struct cm_ll_data *cm_ll_data = &null_cm_ll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* cm_base: base virtual address of the CM IP block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct omap_domain_base cm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct omap_domain_base cm2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CM_NO_CLOCKS		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CM_SINGLE_INSTANCE	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @cm: CM base virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @cm2: CM2 base virtual address (if present on the booted SoC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * XXX Will be replaced when the PRM/CM drivers are completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	cm_base.va = cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	cm2_base.va = cm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * cm_split_idlest_reg - split CM_IDLEST reg addr into its components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @idlest_reg: CM_IDLEST* virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @prcm_inst: pointer to an s16 to return the PRCM instance offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Given an absolute CM_IDLEST register address @idlest_reg, passes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * the PRCM instance offset and IDLEST register ID back to the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * via the @prcm_inst and @idlest_reg_id.  Returns -EINVAL upon error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * or 0 upon success.  XXX This function is only needed until absolute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * register addresses are removed from the OMAP struct clk records.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			u8 *idlest_reg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (!cm_ll_data->split_idlest_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		WARN_ONCE(1, "cm: %s: no low-level function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			  __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 					   idlest_reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	*prcm_inst -= cm_base.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * omap_cm_wait_module_ready - wait for a module to leave idle or standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * @part: PRCM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * @prcm_mod: PRCM module offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * @idlest_reg: CM_IDLESTx register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * Wait for the PRCM to indicate that the module identified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * success, -EBUSY if the module doesn't enable in time, or -EINVAL if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * no per-SoC wait_module_ready() function pointer has been registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * or if the idlest register is unknown on the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			      u8 idlest_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (!cm_ll_data->wait_module_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		WARN_ONCE(1, "cm: %s: no low-level function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			  __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return cm_ll_data->wait_module_ready(part, prcm_mod, idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 					     idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * omap_cm_wait_module_idle - wait for a module to enter idle or standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * @part: PRCM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * @prcm_mod: PRCM module offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * @idlest_reg: CM_IDLESTx register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * Wait for the PRCM to indicate that the module identified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * (@prcm_mod, @idlest_id, @idlest_shift) is no longer clocked.  Return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * 0 upon success, -EBUSY if the module doesn't enable in time, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * -EINVAL if no per-SoC wait_module_idle() function pointer has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * registered or if the idlest register is unknown on the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			     u8 idlest_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (!cm_ll_data->wait_module_idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		WARN_ONCE(1, "cm: %s: no low-level function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			  __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return cm_ll_data->wait_module_idle(part, prcm_mod, idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 					    idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * omap_cm_module_enable - enable a module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * @mode: target mode for the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * @part: PRCM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * @inst: PRCM instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * @clkctrl_offs: CM_CLKCTRL register offset for the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * making its IO space accessible. Return 0 upon success, -EINVAL if no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * per-SoC module_enable() function pointer has been registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!cm_ll_data->module_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		WARN_ONCE(1, "cm: %s: no low-level function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			  __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	cm_ll_data->module_enable(mode, part, inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * omap_cm_module_disable - disable a module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * @part: PRCM partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * @inst: PRCM instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * @clkctrl_offs: CM_CLKCTRL register offset for the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * makings its IO space inaccessible. Return 0 upon success, -EINVAL if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * no per-SoC module_disable() function pointer has been registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (!cm_ll_data->module_disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		WARN_ONCE(1, "cm: %s: no low-level function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			  __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	cm_ll_data->module_disable(part, inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!cm_ll_data->xlate_clkctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		WARN_ONCE(1, "cm: %s: no low-level function defined\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			  __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * cm_register - register per-SoC low-level data with the CM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * @cld: low-level per-SoC OMAP CM data & function pointers to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * Register per-SoC low-level OMAP CM data and function pointers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * the OMAP CM common interface.  The caller must keep the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * pointed to by @cld valid until it calls cm_unregister() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * it returns successfully.  Returns 0 upon success, -EINVAL if @cld
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * is NULL, or -EEXIST if cm_register() has already been called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * without an intervening cm_unregister().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int cm_register(const struct cm_ll_data *cld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (!cld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (cm_ll_data != &null_cm_ll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	cm_ll_data = cld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * cm_unregister - unregister per-SoC low-level data & function pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * @cld: low-level per-SoC OMAP CM data & function pointers to unregister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * Unregister per-SoC low-level OMAP CM data and function pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * that were previously registered with cm_register().  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * caller may not destroy any of the data pointed to by @cld until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * this function returns successfully.  Returns 0 upon success, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * -EINVAL if @cld is NULL or if @cld does not match the struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * cm_ll_data * previously registered by cm_register().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int cm_unregister(const struct cm_ll_data *cld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!cld || cm_ll_data != cld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	cm_ll_data = &null_cm_ll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	defined(CONFIG_SOC_DRA7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct omap_prcm_init_data cm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.index = TI_CLKM_CM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.init = omap4_cm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct omap_prcm_init_data cm2_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.index = TI_CLKM_CM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.init = omap4_cm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef CONFIG_ARCH_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct omap_prcm_init_data omap2_prcm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.index = TI_CLKM_CM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.init = omap2xxx_cm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct omap_prcm_init_data omap3_cm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.index = TI_CLKM_CM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.init = omap3xxx_cm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.flags = CM_SINGLE_INSTANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * IVA2 offset is a negative value, must offset the cm_base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * by this to get it to positive side on the iomap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.offset = -OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct omap_prcm_init_data am3_prcm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.index = TI_CLKM_CM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.init = am33xx_cm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #ifdef CONFIG_SOC_AM43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct omap_prcm_init_data am4_prcm_data __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.index = TI_CLKM_CM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.init = omap4_cm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifdef CONFIG_ARCH_OMAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #ifdef CONFIG_ARCH_OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef CONFIG_ARCH_OMAP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .compatible = "ti,omap4-cm1", .data = &cm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ .compatible = "ti,omap4-cm2", .data = &cm2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #ifdef CONFIG_SOC_OMAP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{ .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ .compatible = "ti,omap5-cm-core", .data = &cm2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #ifdef CONFIG_SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ .compatible = "ti,dra7-cm-core", .data = &cm2_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef CONFIG_SOC_AM33XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #ifdef CONFIG_SOC_AM43XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #ifdef CONFIG_SOC_TI81XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * omap2_cm_base_init - initialize iomappings for the CM drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * Detects and initializes the iomappings for the CM driver, based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  * on the DT data. Returns 0 in success, negative error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  * otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int __init omap2_cm_base_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct omap_prcm_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	struct omap_domain_base *mem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		data = (struct omap_prcm_init_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		if (data->index == TI_CLKM_CM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			mem = &cm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		if (data->index == TI_CLKM_CM2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			mem = &cm2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		data->mem = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		if (mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			mem->pa = res.start + data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			mem->va = data->mem + data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			mem->offset = data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		data->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 				   (cm_base.va && cm2_base.va)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			data->init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  * omap_cm_init - low level init for the CM drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  * Initializes the low level clock infrastructure for CM drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * Returns 0 in success, negative error value in failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int __init omap_cm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	const struct omap_prcm_init_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		if (data->flags & CM_NO_CLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }