Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Clock domain register offsets for TI81XX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* TI81XX common CM module offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TI81XX_CM_ACTIVE_MOD			0x0400	/* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TI81XX_CM_DEFAULT_MOD			0x0500	/* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TI81XX_CM_ALWON_MOD			0x1400	/* 1KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TI81XX_CM_SGX_MOD			0x0900	/* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* TI816X CM module offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TI816X_CM_IVAHD0_MOD			0x0600	/* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TI816X_CM_IVAHD1_MOD			0x0700	/* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TI816X_CM_IVAHD2_MOD			0x0800	/* 256B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* ALWON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TI81XX_CM_ALWON_L3_SLOW_CLKDM		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TI81XX_CM_ALWON_L3_MED_CLKDM		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TI81XX_CM_ETHERNET_CLKDM		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TI81XX_CM_MMU_CLKDM			0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TI81XX_CM_MMUCFG_CLKDM			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TI81XX_CM_ALWON_MPU_CLKDM		0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TI81XX_CM_ALWON_L3_FAST_CLKDM		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ACTIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TI816X_CM_ACTIVE_GEM_CLKDM		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* IVAHD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TI816X_CM_IVAHD0_CLKDM			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* IVAHD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TI816X_CM_IVAHD1_CLKDM			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* IVAHD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TI816X_CM_IVAHD2_CLKDM			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* SGX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TI816X_CM_SGX_CLKDM			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* DEFAULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TI816X_CM_DEFAULT_L3_MED_CLKDM		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TI816X_CM_DEFAULT_PCI_CLKDM		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TI816X_CM_DEFAULT_L3_SLOW_CLKDM		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TI816X_CM_DEFAULT_DUCATI_CLKDM		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TI816X_CM_DEFAULT_SATA_CLKDM		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif