Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP2/3 Clock Management (CM) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2007-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2007-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * The CM hardware modules on the OMAP2/3 are quite similar to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * other.  The CM modules/instances on OMAP4 are quite different, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * they are handled in a separate file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP34XX_CM_REGADDR(module, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * OMAP3-specific global CM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * Use cm_{read,write}_reg() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * These registers appear once per CM module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP3430_CM_SYSCONFIG		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP3430_CM_POLCTRL		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP3430_CM_CLKOUT_CTRL		OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * Module specific CM register offsets from CM_BASE + domain offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * Use cm_{read,write}_mod_reg() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * These register offsets generally appear in more than one PRCM submodule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* OMAP3-specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP3430_CM_CLKEN_PLL				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP3430ES2_CM_CLKEN2				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP3430ES2_CM_FCLKEN3				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP3430_CM_CLKSEL1				CM_CLKSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP3430_CM_CLKSTST				0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP3430ES2_CM_CLKSEL4				0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP3430ES2_CM_CLKSEL5				0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP3430_CM_CLKSEL2_EMU				0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP3430_CM_CLKSEL3_EMU				0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* CM_IDLEST bit field values to indicate deasserted IdleReq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP34XX_CM_IDLEST_VAL				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern void omap3_cm_save_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void omap3_cm_restore_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif