^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP3xxx CM module functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rajendra Nayak <rnayak@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "cm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const u8 omap3xxx_cm_idlest_offs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void _write_clktrctrl(u8 c, s16 module, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) v |= c << __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) v &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) v >>= __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @part: PRCM partition, ignored for OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @prcm_mod: PRCM module offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Wait for the PRCM to indicate that the module identified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * success or -EBUSY if the module doesn't enable in time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 idlest_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ena = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 cm_idlest_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mask = 1 << idlest_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ena = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mask) == ena), MAX_MODULE_READY_TIME, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @idlest_reg: CM_IDLEST* virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @prcm_inst: pointer to an s16 to return the PRCM instance offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * XXX This function is only needed until absolute register addresses are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * removed from the OMAP struct clk records.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int omap3xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) s16 *prcm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 *idlest_reg_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 idlest_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) idlest_offs = idlest_reg->offset & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *idlest_reg_id = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) offs = idlest_reg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) offs &= 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *prcm_inst = offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Clockdomain low-level operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct clockdomain *clkdm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clkdm1->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clockdomain *clkdm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clkdm1->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct clockdomain *clkdm2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) OMAP3430_CM_SLEEPDEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (1 << clkdm2->dep_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct clkdm_dep *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!cd->clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) continue; /* only happens if data is erroneous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mask |= 1 << cd->clkdm->dep_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cd->sleepdep_usecount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (clkdm->usecount > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) clkdm_add_autodeps(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (clkdm->usecount > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clkdm_del_autodeps(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) bool hwsup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!clkdm->clktrctrl_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * more details on the unpleasant problem this is working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) omap3xxx_clkdm_wakeup(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (hwsup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Disable HW transitions when we are changing deps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clkdm_add_autodeps(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) omap3xxx_clkdm_wakeup(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bool hwsup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!clkdm->clktrctrl_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * more details on the unpleasant problem this is working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (hwsup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Disable HW transitions when we are changing deps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clkdm_del_autodeps(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clkdm->clktrctrl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) omap3xxx_clkdm_sleep(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct clkdm_ops omap3_clkdm_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .clkdm_sleep = omap3xxx_clkdm_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .clkdm_wakeup = omap3xxx_clkdm_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .clkdm_allow_idle = omap3xxx_clkdm_allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .clkdm_deny_idle = omap3xxx_clkdm_deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Context save/restore code - OMAP3 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct omap3_cm_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 iva2_cm_clksel1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 iva2_cm_clksel2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 cm_sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 sgx_cm_clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 dss_cm_clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 cam_cm_clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 per_cm_clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 emu_cm_clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 emu_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 pll_cm_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 pll_cm_autoidle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 pll_cm_clksel4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 pll_cm_clksel5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 pll_cm_clken2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 cm_polctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 iva2_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 iva2_cm_clken_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 core_cm_fclken1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 core_cm_fclken3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 sgx_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 wkup_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 dss_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 cam_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 per_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 usbhost_cm_fclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 core_cm_iclken1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 core_cm_iclken2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 core_cm_iclken3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 sgx_cm_iclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 wkup_cm_iclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 dss_cm_iclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 cam_cm_iclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 per_cm_iclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 usbhost_cm_iclken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 iva2_cm_autoidle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 mpu_cm_autoidle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 iva2_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 mpu_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 core_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 sgx_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 dss_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 cam_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 per_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 neon_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 usbhost_cm_clkstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 core_cm_autoidle1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 core_cm_autoidle2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 core_cm_autoidle3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 wkup_cm_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 dss_cm_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 cam_cm_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 per_cm_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 usbhost_cm_autoidle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 sgx_cm_sleepdep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 dss_cm_sleepdep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 cam_cm_sleepdep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 per_cm_sleepdep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 usbhost_cm_sleepdep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 cm_clkout_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct omap3_cm_regs cm_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void omap3_cm_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cm_context.iva2_cm_clksel1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cm_context.iva2_cm_clksel2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cm_context.cm_sysconfig =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cm_context.sgx_cm_clksel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cm_context.dss_cm_clksel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cm_context.cam_cm_clksel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cm_context.per_cm_clksel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cm_context.emu_cm_clksel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cm_context.emu_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * As per erratum i671, ROM code does not respect the PER DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * In this case, even though this register has been saved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * by ourselves. So, we need to save it anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cm_context.pll_cm_autoidle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cm_context.pll_cm_autoidle2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cm_context.pll_cm_clksel4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cm_context.pll_cm_clksel5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cm_context.pll_cm_clken2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cm_context.cm_polctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cm_context.iva2_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cm_context.iva2_cm_clken_pll =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cm_context.core_cm_fclken1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cm_context.core_cm_fclken3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cm_context.sgx_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cm_context.wkup_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cm_context.dss_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cm_context.cam_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cm_context.per_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cm_context.usbhost_cm_fclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cm_context.core_cm_iclken1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cm_context.core_cm_iclken2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) cm_context.core_cm_iclken3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cm_context.sgx_cm_iclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cm_context.wkup_cm_iclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) cm_context.dss_cm_iclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cm_context.cam_cm_iclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) cm_context.per_cm_iclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cm_context.usbhost_cm_iclken =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cm_context.iva2_cm_autoidle2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cm_context.mpu_cm_autoidle2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cm_context.iva2_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cm_context.mpu_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cm_context.core_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cm_context.sgx_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cm_context.dss_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cm_context.cam_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cm_context.per_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cm_context.neon_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cm_context.usbhost_cm_clkstctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cm_context.core_cm_autoidle1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) cm_context.core_cm_autoidle2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cm_context.core_cm_autoidle3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cm_context.wkup_cm_autoidle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cm_context.dss_cm_autoidle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) cm_context.cam_cm_autoidle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) cm_context.per_cm_autoidle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cm_context.usbhost_cm_autoidle =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cm_context.sgx_cm_sleepdep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cm_context.dss_cm_sleepdep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cm_context.cam_cm_sleepdep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cm_context.per_cm_sleepdep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cm_context.usbhost_cm_sleepdep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cm_context.cm_clkout_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) OMAP3_CM_CLKOUT_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) void omap3_cm_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CM_CLKSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CM_CLKSEL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) OMAP3430_CM_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) CM_CLKSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * As per erratum i671, ROM code does not respect the PER DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) OMAP3430ES2_CM_CLKSEL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) OMAP3430ES2_CM_CLKSEL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) OMAP3430ES2_CM_CLKEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) OMAP3430_CM_POLCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) OMAP3430_CM_CLKEN_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CM_FCLKEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) OMAP3430ES2_CM_FCLKEN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) CM_ICLKEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CM_ICLKEN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CM_ICLKEN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) CM_AUTOIDLE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) CM_AUTOIDLE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) CM_AUTOIDLE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) OMAP3_CM_CLKOUT_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) void omap3_cm_save_scratchpad_contents(u32 *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * As per erratum i671, ROM code does not respect the PER DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Then, in any case, clear these bits to avoid extra latencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const struct cm_ll_data omap3xxx_cm_ll_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .split_idlest_reg = &omap3xxx_cm_split_idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .wait_module_ready = &omap3xxx_cm_wait_module_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) OMAP3430_IVA2_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return cm_register(&omap3xxx_cm_ll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static void __exit omap3xxx_cm_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) cm_unregister(&omap3xxx_cm_ll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) __exitcall(omap3xxx_cm_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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