Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * AM33XX CM offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "cm-regbits-33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* CM base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AM33XX_CM_BASE		0x44e00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AM33XX_CM_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* CM instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AM33XX_CM_PER_MOD		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AM33XX_CM_WKUP_MOD		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AM33XX_CM_DPLL_MOD		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AM33XX_CM_MPU_MOD		0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AM33XX_CM_DEVICE_MOD		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AM33XX_CM_RTC_MOD		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AM33XX_CM_GFX_MOD		0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AM33XX_CM_CEFUSE_MOD		0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* CM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* CM.PER_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AM33XX_CM_PER_CPGMAC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AM33XX_CM_PER_LCDC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET		0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AM33XX_CM_PER_USB0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AM33XX_CM_PER_MLB_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AM33XX_CM_PER_TPTC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AM33XX_CM_PER_OCMCRAM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AM33XX_CM_PER_GPMC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AM33XX_CM_PER_MCASP0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AM33XX_CM_PER_UART5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define AM33XX_CM_PER_MMC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AM33XX_CM_PER_ELM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define AM33XX_CM_PER_I2C2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define AM33XX_CM_PER_I2C1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AM33XX_CM_PER_SPI0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AM33XX_CM_PER_SPI1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define AM33XX_CM_PER_SPI2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AM33XX_CM_PER_SPI3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define AM33XX_CM_PER_L4LS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AM33XX_CM_PER_L4FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define AM33XX_CM_PER_MCASP1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AM33XX_CM_PER_UART1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define AM33XX_CM_PER_UART2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AM33XX_CM_PER_UART3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AM33XX_CM_PER_UART4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AM33XX_CM_PER_TIMER7_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AM33XX_CM_PER_TIMER2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AM33XX_CM_PER_TIMER3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AM33XX_CM_PER_TIMER4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AM33XX_CM_PER_MCASP2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AM33XX_CM_PER_RNG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AM33XX_CM_PER_AES0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AM33XX_CM_PER_AES1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AM33XX_CM_PER_DES_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AM33XX_CM_PER_SHA0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET		0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AM33XX_CM_PER_PKA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AM33XX_CM_PER_GPIO6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AM33XX_CM_PER_GPIO1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AM33XX_CM_PER_GPIO2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AM33XX_CM_PER_GPIO3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AM33XX_CM_PER_GPIO4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AM33XX_CM_PER_TPCC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AM33XX_CM_PER_DCAN0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AM33XX_CM_PER_DCAN1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AM33XX_CM_PER_EPWMSS1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AM33XX_CM_PER_EMIF_FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AM33XX_CM_PER_EPWMSS0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AM33XX_CM_PER_EPWMSS2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AM33XX_CM_PER_L3_INSTR_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET			0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AM33XX_CM_PER_L3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET		0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AM33XX_CM_PER_IEEE5000_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AM33XX_CM_PER_PRUSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AM33XX_CM_PER_TIMER5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AM33XX_CM_PER_TIMER6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AM33XX_CM_PER_MMC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AM33XX_CM_PER_MMC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AM33XX_CM_PER_TPTC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AM33XX_CM_PER_TPTC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AM33XX_CM_PER_GPIO5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AM33XX_CM_PER_SPINLOCK_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AM33XX_CM_PER_MAILBOX0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET		0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AM33XX_CM_PER_L4HS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AM33XX_CM_PER_L4HS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET		0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET		0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET		0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AM33XX_CM_PER_OCPWP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET		0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AM33XX_CM_PER_MAILBOX1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET		0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AM33XX_CM_PER_PRUSS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET		0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AM33XX_CM_PER_CPSW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET		0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AM33XX_CM_PER_LCDC_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET		0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET	0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* CM.WKUP_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AM33XX_CM_WKUP_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AM33XX_CM_WKUP_CONTROL_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AM33XX_CM_WKUP_GPIO0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AM33XX_CM_WKUP_TIMER0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AM33XX_CM_L3_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AM33XX_CM_AUTOIDLE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AM33XX_CM_IDLEST_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AM33XX_CM_CLKSEL_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AM33XX_CM_AUTOIDLE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AM33XX_CM_IDLEST_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AM33XX_CM_CLKSEL_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AM33XX_CM_AUTOIDLE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AM33XX_CM_IDLEST_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET	0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET	0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AM33XX_CM_CLKSEL_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AM33XX_CM_AUTOIDLE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET		0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AM33XX_CM_IDLEST_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AM33XX_CM_CLKSEL_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AM33XX_CM_AUTOIDLE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AM33XX_CM_IDLEST_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET	0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET	0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET		0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AM33XX_CM_CLKDCOLDO_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AM33XX_CM_DIV_M4_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET		0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define AM33XX_CM_DIV_M5_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define AM33XX_CM_CLKMODE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AM33XX_CM_CLKMODE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AM33XX_CM_CLKMODE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AM33XX_CM_CLKMODE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AM33XX_CM_CLKMODE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AM33XX_CM_CLKSEL_DPLL_PERIPH			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AM33XX_CM_DIV_M2_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET		0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AM33XX_CM_DIV_M2_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AM33XX_CM_DIV_M2_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AM33XX_CM_DIV_M2_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define AM33XX_CM_WKUP_UART0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AM33XX_CM_WKUP_I2C0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define AM33XX_CM_WKUP_TIMER1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define AM33XX_CM_WKUP_WDT0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define AM33XX_CM_WKUP_WDT1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET		0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define AM33XX_CM_DIV_M6_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* CM.DPLL_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define AM33XX_CLKSEL_TIMER7_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AM33XX_CLKSEL_TIMER2_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET			0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define AM33XX_CLKSEL_TIMER3_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define AM33XX_CLKSEL_TIMER4_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AM33XX_CM_MAC_CLKSEL_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AM33XX_CM_MAC_CLKSEL				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET			0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define AM33XX_CLKSEL_TIMER5_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET			0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define AM33XX_CLKSEL_TIMER6_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define AM33XX_CM_CPTS_RFT_CLKSEL			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define AM33XX_CLKSEL_TIMER1MS_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define AM33XX_CLKSEL_GFX_FCLK_OFFSET			0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define AM33XX_CLKSEL_GFX_FCLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AM33XX_CLKSEL_PRUSS_OCP_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define AM33XX_CLKSEL_LCDC_PIXEL_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AM33XX_CLKSEL_WDT1_CLK_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define AM33XX_CLKSEL_WDT1_CLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define AM33XX_CLKSEL_GPIO0_DBCLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* CM.MPU_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AM33XX_CM_MPU_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define AM33XX_CM_MPU_MPU_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* CM.DEVICE_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AM33XX_CM_CLKOUT_CTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AM33XX_CM_CLKOUT_CTRL				AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* CM.RTC_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define AM33XX_CM_RTC_RTC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define AM33XX_CM_RTC_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* CM.GFX_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define AM33XX_CM_GFX_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AM33XX_CM_GFX_GFX_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AM33XX_CM_GFX_BITBLT_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET	0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1		AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define AM33XX_CM_GFX_MMUCFG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET		0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define AM33XX_CM_GFX_MMUDATA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* CM.CEFUSE_CM register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define AM33XX_CM_CEFUSE_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int am33xx_cm_init(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif /* ASSEMBLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif