^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AM33XX CM functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Reference taken from from OMAP4 cminst44xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "cm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "cm-regbits-33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "prm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 0x0 func: Module is fully functional, including OCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * abortion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * using separate functional clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0x3 disabled: Module is disabled and cannot be accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLKCTRL_IDLEST_FUNCTIONAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKCTRL_IDLEST_INTRANSITION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKCTRL_IDLEST_DISABLED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Private functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Read a register in a CM instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return readl_relaxed(cm_base.va + inst + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Write into a register in a CM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel_relaxed(val, cm_base.va + inst + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Read-modify-write a register in CM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) v = am33xx_cm_read_reg(inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) v |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) am33xx_cm_write_reg(v, inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) v = am33xx_cm_read_reg(inst, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) v &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) v >>= __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * bit 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) v &= AM33XX_IDLEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) v >>= AM33XX_IDLEST_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * _is_module_ready - can module registers be accessed without causing an abort?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) v = _clkctrl_idlest(inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @c must be the unshifted value for CLKTRCTRL - i.e., this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * will handle the shift itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) v = am33xx_cm_read_reg(inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) v &= ~AM33XX_CLKTRCTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) v |= c << AM33XX_CLKTRCTRL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) am33xx_cm_write_reg(v, inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Public functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Returns true if the clockdomain referred to by (@inst, @cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * is in hardware-supervised idle mode, or 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) v = am33xx_cm_read_reg(inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) v &= AM33XX_CLKTRCTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) v >>= AM33XX_CLKTRCTRL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Put a clockdomain referred to by (@inst, @cdoffs) into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * hardware-supervised idle mode. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Put a clockdomain referred to by (@inst, @cdoffs) into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * software-supervised idle mode, i.e., controlled manually by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Linux OMAP clockdomain code. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Put a clockdomain referred to by (@inst, @cdoffs) into idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * waking it up. No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @part: PRCM partition, ignored for AM33xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @bit_shift: bit shift for the register, ignored for AM33xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Wait for the module IDLEST to be functional. If the idle state is in any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * the non functional state (trans, idle or disabled), module and thus the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * sysconfig cannot be accessed and will probably lead to an "imprecise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * external abort"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 bit_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MAX_MODULE_READY_TIME, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @part: CM partition, ignored for AM33xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @bit_shift: bit shift for the register, ignored for AM33xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Wait for the module IDLEST to be disabled. Some PRCM transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * like reset assertion or parent clock de-activation must wait the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * module to be fully disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 bit_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CLKCTRL_IDLEST_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MAX_MODULE_READY_TIME, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @mode: Module mode (SW or HW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @part: CM partition, ignored for AM33xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) v = am33xx_cm_read_reg(inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) v &= ~AM33XX_MODULEMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) v |= mode << AM33XX_MODULEMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) am33xx_cm_write_reg(v, inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * am33xx_cm_module_disable - Disable the module inside CLKCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @part: CM partition, ignored for AM33xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @inst: CM instance register offset (*_INST macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) v = am33xx_cm_read_reg(inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) v &= ~AM33XX_MODULEMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) am33xx_cm_write_reg(v, inst, clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Clockdomain low-level functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return am33xx_clkdm_wakeup(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) bool hwsup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) am33xx_clkdm_sleep(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return cm_base.pa + inst + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * am33xx_clkdm_save_context - Save the clockdomain transition context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @clkdm: The clockdomain pointer whose context needs to be saved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Save the clockdomain transition context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int am33xx_clkdm_save_context(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clkdm->context = am33xx_cm_read_reg_bits(clkdm->cm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clkdm->clkdm_offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) AM33XX_CLKTRCTRL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * am33xx_restore_save_context - Restore the clockdomain transition context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @clkdm: The clockdomain pointer whose context needs to be restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Restore the clockdomain transition context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int am33xx_clkdm_restore_context(struct clockdomain *clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) switch (clkdm->context) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case OMAP34XX_CLKSTCTRL_DISABLE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) am33xx_clkdm_deny_idle(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case OMAP34XX_CLKSTCTRL_FORCE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) am33xx_clkdm_sleep(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case OMAP34XX_CLKSTCTRL_FORCE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) am33xx_clkdm_wakeup(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case OMAP34XX_CLKSTCTRL_ENABLE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) am33xx_clkdm_allow_idle(clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct clkdm_ops am33xx_clkdm_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clkdm_sleep = am33xx_clkdm_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .clkdm_wakeup = am33xx_clkdm_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .clkdm_allow_idle = am33xx_clkdm_allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .clkdm_deny_idle = am33xx_clkdm_deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .clkdm_clk_enable = am33xx_clkdm_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .clkdm_clk_disable = am33xx_clkdm_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .clkdm_save_context = am33xx_clkdm_save_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .clkdm_restore_context = am33xx_clkdm_restore_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct cm_ll_data am33xx_cm_ll_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .wait_module_ready = &am33xx_cm_wait_module_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .wait_module_idle = &am33xx_cm_wait_module_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .module_enable = &am33xx_cm_module_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .module_disable = &am33xx_cm_module_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .xlate_clkctrl = &am33xx_cm_xlate_clkctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return cm_register(&am33xx_cm_ll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void __exit am33xx_cm_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cm_unregister(&am33xx_cm_ll_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) __exitcall(am33xx_cm_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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