^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2/3 Clock Management (CM) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The CM hardware modules on the OMAP2/3 are quite similar to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * other. The CM modules/instances on OMAP4 are quite different, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * they are handled in a separate file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Module specific CM register offsets from CM_BASE + domain offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Use cm_{read,write}_mod_reg() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * These register offsets generally appear in more than one PRCM submodule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Common between OMAP2 and OMAP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CM_FCLKEN 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CM_FCLKEN1 CM_FCLKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CM_CLKEN CM_FCLKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CM_ICLKEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CM_ICLKEN1 CM_ICLKEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CM_ICLKEN2 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CM_ICLKEN3 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CM_IDLEST 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CM_IDLEST1 CM_IDLEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CM_IDLEST2 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP2430_CM_IDLEST3 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CM_AUTOIDLE 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CM_AUTOIDLE1 CM_AUTOIDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CM_AUTOIDLE2 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CM_AUTOIDLE3 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CM_CLKSEL 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CM_CLKSEL1 CM_CLKSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CM_CLKSEL2 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP2_CM_CLKSTCTRL 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return readl_relaxed(cm_base.va + module + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel_relaxed(val, cm_base.va + module + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Read-modify-write a register in a CM module. Caller must lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) v = omap2_cm_read_mod_reg(module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) v &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) v |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) omap2_cm_write_mod_reg(v, module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Read a CM register, AND it, and shift the result down to bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) v = omap2_cm_read_mod_reg(domain, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) v &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) v >>= __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern int omap2xxx_cm_apll54_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern void omap2xxx_cm_apll54_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extern int omap2xxx_cm_apll96_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern void omap2xxx_cm_apll96_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* CM register bits shared between 24XX and 3430 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* CM_CLKSEL_GFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP_CLKSEL_GFX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP_CLKSEL_GFX_WIDTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* CM_ICLKEN_GFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP_EN_GFX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP_EN_GFX_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* CM_IDLEST_GFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP_ST_GFX_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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