Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP2xxx Clock Management (CM) register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2007-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * The CM hardware modules on the OMAP2/3 are quite similar to each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * other.  The CM modules/instances on OMAP4 are quite different, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * they are handled in a separate file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP2420_CM_REGADDR(module, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP2430_CM_REGADDR(module, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * Module specific CM register offsets from CM_BASE + domain offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * Use cm_{read,write}_mod_reg() with these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * These register offsets generally appear in more than one PRCM submodule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* OMAP2-specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP24XX_CM_FCLKEN2				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP24XX_CM_ICLKEN4				0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP24XX_CM_AUTOIDLE4				0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP24XX_CM_IDLEST4				0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* CM_IDLEST bit field values to indicate deasserted IdleReq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP24XX_CM_IDLEST_VAL				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Clock management domain register get/set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 				  u8 idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern int omap2xxx_cm_fclks_active(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern int omap2xxx_cm_mpu_retention_allowed(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern u32 omap2xxx_cm_get_core_clk_src(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern u32 omap2xxx_cm_get_core_pll_config(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 					 u32 mdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif