Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRA7xx CM2 instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* CM2 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRA7XX_CM_CORE_BASE		0x4a008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DRA7XX_CM_CORE_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* CM_CORE instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRA7XX_CM_CORE_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DRA7XX_CM_CORE_CKGEN_INST	0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DRA7XX_CM_CORE_COREAON_INST	0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DRA7XX_CM_CORE_CORE_INST	0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DRA7XX_CM_CORE_IVA_INST		0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DRA7XX_CM_CORE_CAM_INST		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRA7XX_CM_CORE_DSS_INST		0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DRA7XX_CM_CORE_GPU_INST		0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DRA7XX_CM_CORE_L3INIT_INST	0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DRA7XX_CM_CORE_CUSTEFUSE_INST	0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DRA7XX_CM_CORE_L4PER_INST	0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DRA7XX_CM_CORE_RESTORE_INST	0x1e18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* CM_CORE clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS			0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS			0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS			0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS		0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS		0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS		0x01fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS		0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* CM_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DRA7XX_REVISION_CM_CORE_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET				0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* CM_CORE.CKGEN_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DRA7XX_CM_CLKSEL_USB_60MHZ				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET			0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DRA7XX_CM_CLKMODE_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DRA7XX_CM_IDLEST_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET			0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DRA7XX_CM_AUTOIDLE_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET			0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DRA7XX_CM_CLKSEL_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET			0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DRA7XX_CM_DIV_M2_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DRA7XX_CM_DIV_M3_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET			0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DRA7XX_CM_DIV_H11_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DRA7XX_CM_DIV_H12_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET			0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DRA7XX_CM_DIV_H13_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DRA7XX_CM_DIV_H14_DPLL_PER				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET			0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DRA7XX_CM_CLKMODE_DPLL_USB				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRA7XX_CM_IDLEST_DPLL_USB				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET			0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRA7XX_CM_AUTOIDLE_DPLL_USB				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRA7XX_CM_CLKSEL_DPLL_USB				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET			0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRA7XX_CM_DIV_M2_DPLL_USB				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET			0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRA7XX_CM_CLKDCOLDO_DPLL_USB				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET			0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET			0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET			0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET			0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET		0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET		0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET			0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DRA7XX_CM_CLKMODE_APLL_PCIE				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET			0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DRA7XX_CM_IDLEST_APLL_PCIE				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET			0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRA7XX_CM_DIV_M2_APLL_PCIE				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET			0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* CM_CORE.COREAON_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET	0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET	0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET	0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET	0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET	0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* CM_CORE.CORE_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET			0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET			0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET	0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET	0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET	0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET				0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DRA7XX_CM_IPU2_STATICDEP_OFFSET				0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET			0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET			0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DRA7XX_CM_IPU2_IPU2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET				0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DRA7XX_CM_DMA_STATICDEP_OFFSET				0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET				0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET			0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET				0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET			0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DRA7XX_CM_EMIF_DMM_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET		0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET			0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET			0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET			0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET			0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DRA7XX_CM_ATL_ATL_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET				0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET			0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET			0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET			0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET			0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET			0x0638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET			0x0640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET			0x0648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET			0x0650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET			0x0658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET			0x0660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET			0x0668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET			0x0670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET			0x0678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET			0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET		0x0688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET		0x0690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET		0x0698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET		0x06a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET	0x06a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET	0x06b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET	0x06b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET		0x06c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET			0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET		0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET		0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET		0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET		0x0748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET	0x0750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* CM_CORE.IVA_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DRA7XX_CM_IVA_STATICDEP_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DRA7XX_CM_IVA_IVA_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRA7XX_CM_IVA_SL2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* CM_CORE.CAM_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRA7XX_CM_CAM_STATICDEP_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRA7XX_CM_CAM_VIP1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRA7XX_CM_CAM_VIP2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRA7XX_CM_CAM_VIP3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DRA7XX_CM_CAM_CSI1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET			0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRA7XX_CM_CAM_CSI2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* CM_CORE.DSS_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DRA7XX_CM_DSS_STATICDEP_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DRA7XX_CM_DSS_DSS_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DRA7XX_CM_DSS_BB2D_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET			0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DRA7XX_CM_DSS_SDVENC_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* CM_CORE.GPU_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRA7XX_CM_GPU_STATICDEP_OFFSET				0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRA7XX_CM_GPU_GPU_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* CM_CORE.L3INIT_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRA7XX_CM_L3INIT_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DRA7XX_CM_L3INIT_SATA_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET				0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DRA7XX_CM_PCIE_STATICDEP_OFFSET				0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET			0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET			0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET				0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DRA7XX_CM_GMAC_STATICDEP_OFFSET				0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET			0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET			0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DRA7XX_CM_GMAC_GMAC_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET		0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL		DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* CM_CORE.L4PER_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET			0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET			0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET			0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DRA7XX_CM_L4PER_ELM_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET			0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET			0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET			0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET			0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET			0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DRA7XX_CM_L4PER_I2C1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET			0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DRA7XX_CM_L4PER_I2C2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET			0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DRA7XX_CM_L4PER_I2C3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET			0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DRA7XX_CM_L4PER_I2C4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET			0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET			0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET			0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET			0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET			0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET			0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET			0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET			0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET			0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET			0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET			0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DRA7XX_CM_L4PER_MMC3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET			0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DRA7XX_CM_L4PER_MMC4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET			0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET			0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET			0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DRA7XX_CM_L4PER_UART1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET			0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DRA7XX_CM_L4PER_UART2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET			0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define DRA7XX_CM_L4PER_UART3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET			0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define DRA7XX_CM_L4PER_UART4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET			0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET			0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET			0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define DRA7XX_CM_L4PER_UART5_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET			0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET			0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define DRA7XX_CM_L4SEC_STATICDEP_OFFSET			0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET			0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET			0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET			0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET			0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DRA7XX_CM_L4SEC_AES1_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET			0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DRA7XX_CM_L4SEC_AES2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET			0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET			0x01b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET			0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DRA7XX_CM_L4SEC_RNG_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET			0x01c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET			0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DRA7XX_CM_L4PER2_UART7_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET		0x01d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET			0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DRA7XX_CM_L4PER2_UART8_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET			0x01e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DRA7XX_CM_L4PER2_UART9_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET			0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET			0x01f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL			DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET			0x01fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET			0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET			0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL				DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DRA7XX_CM_L4PER2_STATICDEP_OFFSET			0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET			0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET			0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif